An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Subthreshold Current ◽  
The Poisson Equation ◽  
Strong Inversion ◽  
Cylindrical Form ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Good Agreement

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET

2018 ◽  
Vol 55 ◽  
pp. 75-81 ◽  
Author(s):  
C. Usha ◽  
Palanichamy Vimala
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Fully Depleted ◽  
Metal Work Function ◽  
Surrounding Gate ◽  
Effect Transistor ◽  
Tcad Simulation ◽  
Silicon Thickness ◽  
Metal Work

In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.

Explicit Quantum Drain Current Model for Symmetric Double Gate MOSFETs

2020 ◽  
Vol 61 ◽  
pp. 88-96
Author(s):  
Palanichamy Vimala ◽  
N.R. Nithin Kumar
Keyword(s):  
Charge Density ◽  
Current Model ◽  
Mathematical Expression ◽  
Drain Current ◽  
Quantum Effects ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Quantum Model ◽  
Double Gate ◽  
Inversion Charge

In this article, an analytical model for Double gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) is developed including Quantum effects. The Schrodinger–Poisson’s equation is used to develop the analytical Quantum model using Variational method. A mathematical expression for inversion charge density is obtained and the model was developed with quantum effects by means of oxide capacitance for different channel thickness and gate oxide thickness. Based on inversion charge density model the compact model is developed for transfer characteristics, transconductance and C-V curves of DG MOSFETs. The results of the model are compared to the simulated results. The comparison shows the accuracy of the proposed model.

scholarly journals Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Device Structure ◽  
Band Engineering ◽  
Novel Device ◽  
Analytical Potential ◽  
Good Agreement

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

scholarly journals Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

2021 ◽  
Vol 55 (4) ◽  
pp. 355
Author(s):  
Sanjay ◽  
B. Prasad ◽  
A. Vohra
Keyword(s):  
Drain Current ◽  
Gate Length ◽  
Inversion Mode ◽  
Surrounding Gate ◽  
Consistent Solution ◽  
Gate Engineering ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Silicon Nanotube ◽  
Non Equilibrium Green’S Function

In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green's function (NEGF) approach and self-consistent solution of Poisson's equation with Schrodinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO2) thickness on ID has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG CGAA SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same IOn current as IM device and (ii) to get the same threshold voltage VTh as IM. This has resulted in 102 and 103 times smaller IOff in matching IOn and VTh optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL ~15 mV/V, almost an ideal SS ~60 mV/dec, and higher IOn/IOff ratio ~2.18·108 as compared to available CGAA literature results. Keywords: inversion mode, junctionless, DM DSG, Si nanotube MOSFET, NEGF, ID, SS, DIBL.

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