An Alternative Test Method for the Dual Port SRAM Memory through the Designware SATA AHCI Implementation in 3-D IC Structures

2021 ◽  
Vol 14 ◽  
Author(s):  
Chandrashekhar Virupakshagouda Patil ◽  
Suma Suryanarayana Suryanarayana
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Test Method ◽  
Advanced Technology ◽  
Process Technology ◽  
Test Environment ◽  
Test Methodology ◽  
Serial Advanced Technology Attachment ◽  
Test Vectors ◽  
Dual Port Memories

Background: It is being considered that conventional methods for testing the dual port memories might not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures due to the presence of the limited test vectors with heterogeneous integration. Objective: Find out a novel test methodology DPRAMs in 3-D IC structures. Methods: This paper has taken the approach called as Application Specific Integrated Chips(ASIC) to gain insights on Front-End behavioral testing and Back-End routability of the dual port memories integrated with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation is using commercially available dual port memories from two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI) is based on the Serial Advanced Technology Attachment (SATA 2.6), AHCI host and external SATA (eSATA) standard bus architecture and being used with My_foundry’s 14nm Low Power (14LP) process technology for logical and physical implementations. Results: This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment. Conclusion: It is being considered that the approach described here might be used as a tool/environment for evaluating any vendor's DPRAMs/2Ports RAMs/2Ports Register Files. As a result, it offers an alternative to the traditional test methodology.

scholarly journals An alternative test method for the dual-port SRAM through the DesignWare SATA AHCI implementation in 3-D IC structures

2021 ◽  
Author(s):  
Chandrashekhar V. Patil ◽  
Suma M. S
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Random Access ◽  
Test Method ◽  
Advanced Technology ◽  
Test Environment ◽  
Serial Advanced Technology Attachment ◽  
And Performance ◽  
Test Vectors ◽  
Dual Port Memories

Abstract The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.

TSV Manufacturing Fault Modeling and Diagnosis Based on Multi-Tone Dither

2019 ◽  
Vol 23 (1) ◽  
pp. 42-51 ◽  
Author(s):  
Yuling Shang ◽  
Min Tan ◽  
Chunquan Li ◽  
Liyuan Sun ◽  
◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Test Method ◽  
Design For Test ◽  
Characteristic Analysis ◽  
Passive Components ◽  
Tone Signal ◽  
Three Dimensional Integrated Circuit ◽  
Rf Signal ◽  
Effective Design

The faults in through-silicon via (TSV) have a critical impact on the reliability and yield of a three-dimensional integrated circuit (3-D IC). With the significant increase in the number of TSVs used in 3-D IC, the testing of TSVs for manufacturing faults poses certain serious challenges especially weak fault testing, and therefore it is important to have effective Design-For-Test (DFT) techniques. In this paper, we present a method for TSV testing using multi-tone dither signal, based on electrical characteristic analysis. This method mainly observes the differences in the root mean square (RMS) value of the output signal voltage between faultless and faulty TSV circuits to detect manufacturing faults, and uses only passive components such as metal lines, without consuming additional power for the testing. With regard to the common manufacturing faults such as voids and pinholes, the electrical characteristics of faulty TSVs are modeled and analyzed, and analytic equations of the faults, which are based on characteristic parameters, are explored. The ground-signal-TSV (GS-TSV) equivalent electrical model with manufacturing faults is simulated and tested by using a multi-tone dither test signal, which is generated by modulating an RF signal with an optimized multi-tone signal. The peak-to-average ratio (PAR) is used as the test evaluation parameter to determine the type and size of the fault. The simulation results demonstrate the effectiveness of the multi-tone dither test method in the detection of voids (as low as ohm level) and pinholes (up to mega ohm level). It is obvious that this method performs better in the diagnosis of weak manufacturing faults in TSVs.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Evaluation of the Resistance of Individual Si Die to Cracking

1998 ◽  
Author(s):  
R. Berriche ◽  
R.K. Lowry ◽  
M.I. Rosenfield
Keyword(s):  
Thermal Cycling ◽  
Hardness Test ◽  
Mechanical Stresses ◽  
Test Method ◽  
Processing Conditions ◽  
Micro Hardness ◽  
Test Methodology ◽  
Vickers Micro Hardness

Abstract The present work investigated the use of the Vickers micro-hardness test method to determine the resistance of individual die to cracking. The results are used as an indicator of resistance to failure under the thermal and mechanical stresses of packaging and subsequent thermal cycling. Indentation measurements on die back surfaces are used to determine how changes in wafer backside processing conditions affect cracks that form around impressions produced at different loads. Test methodology and results obtained at different processing conditions are discussed.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

Determination of Steady-State Adhesive Wear Rate

2005 ◽  
Author(s):  
L. J. Yang
Keyword(s):  
Steady State ◽  
Wear Rate ◽  
Wear Test ◽  
Standard Test ◽  
Test Method ◽  
Testing Time ◽  
Wear Coefficient ◽  
Wear Rates ◽  
Test Methodology

Wear rates obtained from different investigators could vary significantly due to lack of a standard test method. A test methodology is therefore proposed in this paper to enable the steady-state wear rate to be determined more accurately, consistently, and efficiently. The wear test will be divided into four stages: (i) to conduct the transient wear test; (ii) to predict the steady-state wear coefficient with the required sliding distance based on the transient wear data by using Yang’s second wear coefficient equation; (iii) to conduct confirmation runs to obtain the measured steady-state wear coefficient value; and (iv) to convert the steady-state wear coefficient value into a steady-state wear rate. The proposed methodology is supported by wear data obtained previously on aluminium based matrix composite materials. It is capable of giving more accurate steady-state wear coefficient and wear rate values, as well as saving a lot of testing time and labour, by reducing the number of trial runs required to achieve the steady-state wear condition.

Three dimensional dielectrophoretic assembly of singlewalled carbon nanotubes for integrated circuit interconnects

2007 ◽  
Author(s):  
Nishant Khanduja ◽  
Selvapraba Selvarasah ◽  
Prashanth Makaram ◽  
Chia-Ling Chen ◽  
Ahmed Busnaina ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Integrated Circuit ◽  
Three Dimensional

Design on Hierarchical Testing System for Unmanned Ground Vehicles

2011 ◽  
Vol 346 ◽  
pp. 817-822 ◽  
Author(s):  
Xin Li ◽  
Guang Ming Xiong ◽  
Yang Sun ◽  
Shao Bin Wu ◽  
Jian Wei Gong ◽  
...  
Keyword(s):  
Evaluation System ◽  
Test System ◽  
Unmanned Vehicles ◽  
Intelligent Vehicles ◽  
Test Method ◽  
Unmanned Ground Vehicles ◽  
Ground Vehicles ◽  
Test Environment ◽  
Test And Evaluation ◽  
Comprehensive Test

The test system for technical abilities of unmanned vehicles is gradually developed from the single test to comprehensive test. The pre-established test and evaluation system can promote the development of unmanned ground vehicles. The 2009 Future Challenge: Intelligent Vehicles and Beyond (FC’09) pushed China's unmanned vehicles out of laboratories. This paper proposed to design a more scientific and comprehensive test system for future competitions to better guide and regulate the development of China's unmanned vehicles. According to the design idea of stage by stage and level by level, the hierarchical test content from simple to advanced, from local to overall is designed. Then the hierarchic test environment is established according to the levels of test content. The test method based on multi-platform and multi-sensor is put forward to ensure the accuracy of test results. The testing criterion framework is set up to regulate future unmanned vehicle contests and to assess the unmanned vehicles scientifically and accurately.

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