Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)

Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.

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Mind-Shift: An Method for Power and Energy Reduction inApplication Mapping onto Network-o-Chip architectures

10.21203/rs.3.rs-841863/v1 ◽

2021 ◽

Author(s):

yasin asadi

Keyword(s):

Efficient Design ◽

Improved Method ◽

New Approach ◽

Current Design ◽

One Step ◽

Ip Cores ◽

Iot Devices ◽

On Chip ◽

Power And Energy ◽

Designing Method

Abstract Network-on-chip (NoC) is an efficient interconnection designing method for solving the limitations of buses in connecting IP cores. Power consumption is one of the most important issues in this area, solving this problem can lead to a more reliable and efficient design of NoC. Besides, there is another problem which is the More’s law is reaching an end. In this paper, we used a new approach, which improves designing points, so we can design NoC architecture more efficiently based on previous designs. Briefly, this method adds one step before the overall change of architecture which tests if the current design can be improved if we change some internal characteristics. For validation, we applied this method by using wire NoC, and changing its bottlenecks, and make them more efficient by using mapping and adding antennas for wireless communication. While this method seems simple at the first sight, but the result can help many designing, which are vital for industries, and technologies like Wireless Sensor Networks (WSN) and Internet of Things (IoT) devices. Briefly, this method can be used in NoC architectures and make them more efficient in a new style for new purposes. The results compared with the basic designing method with the new improved method; power and Energy improvements are respectively 25% and 46% with mapping and wireless improvements and approximately 60% more than traditional NoC in comparison with the basic method in this approach. This method also paves the way for green computing by avoiding producing more chemicals and products from a reusability perspective.

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Verification of Wishbone Bus Interface for SoC using System Verilog and UVM

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2021.36282 ◽

2021 ◽

Vol 9 (VII) ◽

pp. 158-163

Author(s):

Pooja. D. R

Keyword(s):

Test Bench ◽

System On Chip ◽

Functional Coverage ◽

Design Cycle ◽

System Requirements ◽

Ip Cores ◽

On Chip ◽

Verification Methodology

The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.

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All Internal Thoracic Artery Composite Graft Revascularization

Asian Cardiovascular and Thoracic Annals ◽

10.1177/021849230501300413 ◽

2005 ◽

Vol 13 (4) ◽

pp. 357-360

Author(s):

Hiroshi Izumoto ◽

Kazuaki Ishihara ◽

Tetsunori Kawase ◽

Takayuki Nakajima ◽

Hiroshi Satoh ◽

...

Keyword(s):

Internal Thoracic Artery ◽

Coronary Vessels ◽

Composite Graft ◽

Entire Group ◽

Efficient Design ◽

Technical Feasibility ◽

Left Internal Thoracic Artery ◽

Composite Grafts ◽

Artery Graft ◽

The Right

The aim of this study was to determine the most efficient design of composite grafts and clarify the technical feasibility rate of composite grafting using internal thoracic artery exclusively in patients undergoing triple-vessel revascularization. Retrospective analysis of 104 consecutive patients was carried out. An in situ left internal thoracic artery graft for the left anterior descending artery area, with attachment of the right internal thoracic artery to the side of the left internal thoracic artery to revascularize the circumflex and right coronary vessels, was the most efficient graft design. The technical feasibility rate was 80% (83/104 patients). The mean number of distal anastomoses for the entire group was 3.8 ± 0.8 per patient. Intraoperative left internal thoracic artery flow rate was 91.6 ± 37.8 mL·min−1. With more experience, it is thought that the technical feasibility rate could be increased.

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Energy Efficient Design of Static Asymmetric Low Swing On-Chip Interconnect Circuits

International Journal of Computer Applications ◽

10.5120/13940-1927 ◽

2013 ◽

Vol 80 (15) ◽

pp. 33-35

Author(s):

S. Rajendar ◽

P. Chandrasekhar ◽

M. Asha Rani ◽

B. K. Pradeep Kumar Reddy

Keyword(s):

Energy Efficient ◽

Efficient Design ◽

Energy Efficient Design ◽

On Chip ◽

Interconnect Circuits

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Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System

2006 IEEE International Symposium on Industrial Electronics ◽

10.1109/isie.2006.296126 ◽

2006 ◽

Cited By ~ 1

Author(s):

J. Becker ◽

C. Bieser ◽

J. Becker ◽

K.-d. Mueller-Glaser

Keyword(s):

Rapid Prototyping ◽

Packet Switching ◽

Network On Chip ◽

Switching Algorithm ◽

On Chip ◽

Rapid Prototyping System

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Low-Power FPGA Architecture Based Monitoring Applications in Precision Agriculture

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11040039 ◽

2021 ◽

Vol 11 (4) ◽

pp. 39

Author(s):

Amine Saddik ◽

Rachid Latif ◽

Abdelhafid El Ouardi

Keyword(s):

Precision Agriculture ◽

Agricultural Fields ◽

Vegetation Monitoring ◽

Computing Power ◽

Monitoring Applications ◽

Aerial Vehicle ◽

On Chip ◽

The Right ◽

Power And Energy ◽

Monitoring Algorithm

Today’s on-chip systems technology has grounded impressive advances in computing power and energy consumption. The choice of the right architecture depends on the application. In our case, we were studying vegetation monitoring algorithms in precision agriculture. This study presents a system based on a monitoring algorithm for agricultural fields, an electronic architecture based on a CPU-FPGA SoC system and the OpenCL parallel programming paradigm. We focused our study on our own dataset of agricultural fields to validate the results. The fields studied in our case are in the Guelmin-Oued noun region in the south of Morocco. These fields are divided into two areas, with a total surface of 3.44 Ha2 for the first field and 3.73 Ha2 for the second. The images were collected using a DJI-type unmanned aerial vehicle and an RGB camera. Performance evaluation showed that the system could process up to 86 fps versus 12 fps or 20 fps in C/C++ and OpenMP implementations, respectively. Software optimizations have increased the performance to 107 fps, which meets real-time constraints.

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Advanced Technologies for Transient Faults Detection and Compensation

Design and Test Technology for Dependable Systems-on-Chip - Advances in Computer and Electrical Engineering ◽

10.4018/978-1-60960-212-3.ch006 ◽

2011 ◽

pp. 132-154

Author(s):

Matteo Sonza Reorda ◽

Luca Sterpone ◽

Massimo Violante

Keyword(s):

Market Failure ◽

Propagation Mechanism ◽

Transient Faults ◽

Niche Markets ◽

Time Redundancy ◽

Ip Cores ◽

On Chip ◽

Manufacturing Technologies ◽

Processor Cores ◽

Nuclear Applications

Transient faults became an increasing issue in the past few years as smaller geometries of newer, highly miniaturized, silicon manufacturing technologies brought to the mass-market failure mechanisms traditionally bound to niche markets as electronic equipments for avionic, space or nuclear applications. This chapter presents the origin of transient faults, it discusses the propagation mechanism, it outlines models devised to represent them and finally it discusses the state-of-the-art design techniques that can be used to detect and correct transient faults. The concepts of hardware, data and time redundancy are presented, and their implementations to cope with transient faults affecting storage elements, combinational logic and IP-cores (e.g., processor cores) typically found in a System-on-Chip are discussed.

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Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2309 ◽

2011 ◽

Vol 2 (3) ◽

pp. 111-118 ◽

Cited By ~ 1

Author(s):

Rehan Maroofi ◽

Nitnaware ◽

Limaye

Keyword(s):

Network On Chip ◽

Efficient Design ◽

On Chip ◽

Area Efficient

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Modelling the OFDM-based PHY Layer in SoC for Visible Light Communication

International Journal of Recent Contributions from Engineering Science & IT (iJES) ◽

10.3991/ijes.v7i3.10695 ◽

2019 ◽

Vol 7 (3) ◽

pp. 79

Author(s):

Erwin Setiawan ◽

Trio Adiono ◽

Syifaul Fuada

Keyword(s):

Visible Light ◽

Data Exchange ◽

Visible Light Communication ◽

System On Chip ◽

Matlab Simulation ◽

Industry Standard ◽

Receiver Block ◽

Phy Layer ◽

Ip Cores ◽

On Chip

In this paper, we report a System-on-Chip (SoC) architecture for OFDM-based Visible Light Communication (VLC). The OFDM block was implemented as VLC PHY layer. The OFDM block comprises of transmitter and receiver. In transmitter block, there are Reed-Solomon encoder, modulator, IFFT, and preamble generator. While in receiver block, there are Reed-Solomon decoder, demodulator, FFT, and synchronizer. In SoC, these blocks are designed as IP cores. The industry standard AXI4-Stream protocol was used for data exchange between IP cores. The OFDM model in SoC was verified by comparing with a MATLAB simulation.

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