scholarly journals DESIGN OF CMOS LOW DROP-OUT REGULATORS: A COMPARATIVE STUDY

2013 ◽  
Vol 4 (2) ◽  
pp. 324-330
Author(s):  
Ashvani Kumar Mishra ◽  
Rishikesh Pandey
Keyword(s):  
Comparative Study ◽  
High Precision ◽  
High Performance ◽  
Drop Out ◽  
Portable Devices ◽  
Challenging Problem ◽  
Supply Voltages

The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators. Low Drop-Out Regulators showed advantage over its counterpart. The design of Low Drop-Out Regulators with high performance and less Die area is challenging problem now-a-days. This paper is a study of various techniques that are used to achieve better performance of low drop-out regulators. 

scholarly journals Design and Simulation of a Capless Low Drop Out Voltage Regulator

2021 ◽  
pp. 69-75
Author(s):  
Babitha S ◽  
Mr. Hemanth Naidu K J ◽  
Mr. Ashwin Goutham G ◽  
Mr. Harshith S V
Keyword(s):  
High Performance ◽  
Primary Source ◽  
Operating Conditions ◽  
Drop Out ◽  
Voltage Regulator ◽  
Portable Devices ◽  
Current Amplifier ◽  
Power Resources ◽  
Error Amplifier ◽  
The Stability

Portable electronic devices mostly used battery as their primary source for operation hence longer running batteries or Power resources or vital for any portable device need for stable voltage supplies have led to the development of low dropout voltage regulators low dropout regulators provide stable regulated output voltage in various operating conditions which makes it useful in portable devices that design of high performance and stable low dropout voltage regulator is a challenge nowadays with decreasing device size and increasing power densities. The proposed circuit used a 5pack architecture of error amplifier. This paper proposes the study of behavior of the LDO voltage regulator with internal capacitors i.e., capless. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V obtained dropout voltage of 400mv with the delay of 12.77micro sec, power consumed 1.816W. The proposed design produced DC gain of 31.77db,with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the Cadence 180nm technology. The architecture provides a stable gain and plot for both Temperature and Load Variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Influence of Tooth Errors and Truing Principles of Grinding Wheel Abrasion for Machining Arc Enveloping Worm

2013 ◽  
Vol 652-654 ◽  
pp. 2153-2158
Author(s):  
Wu Ji Jiang ◽  
Jing Wei
Keyword(s):  
Mathematical Model ◽  
Case Studies ◽  
High Precision ◽  
High Performance ◽  
New Method ◽  
Grinding Wheel ◽  
Grinding Process ◽  
The Mathematical Model

Controlling the tooth errors induced by the variation of diameter of grinding wheel is the key problem in the process of ZC1 worm grinding. In this paper, the influence of tooth errors by d1, m and z1 as the grinding wheel diameter changes are analyzed based on the mathematical model of the grinding process. A new mathematical model and truing principle for the grinding wheel of ZC1 worm is presented. The shape grinding wheel truing of ZC1 worm is carried out according to the model. The validity and feasibility of the mathematical model is proved by case studies. The mathematical model presented in this paper provides a new method for reducing the tooth errors of ZC1 worm and it can meet the high-performance and high-precision requirements of ZC1 worm grinding.

scholarly journals Comparative Study of Discrete Component Realizations of Fractional-Order Capacitor and Inductor Active Emulators

2018 ◽  
Vol 27 (11) ◽  
pp. 1850170 ◽  
Author(s):  
Georgia Tsirimokou ◽  
Aslihan Kartci ◽  
Jaroslav Koton ◽  
Norbert Herencsar ◽  
Costas Psychalinos
Keyword(s):  
Comparative Study ◽  
Fractional Order ◽  
High Performance ◽  
Continued Fraction ◽  
Transfer Functions ◽  
Operational Amplifiers ◽  
Current Conveyors ◽  
Continued Fraction Expansion ◽  
Current Feedback ◽  
Discrete Component

Due to the absence of commercially available fractional-order capacitors and inductors, their implementation can be performed using fractional-order differentiators and integrators, respectively, combined with a voltage-to-current conversion stage. The transfer function of fractional-order differentiators and integrators can be approximated through the utilization of appropriate integer-order transfer functions. In order to achieve that, the Continued Fraction Expansion as well as the Oustaloup’s approximations can be utilized. The accuracy, in terms of magnitude and phase response, of transfer functions of differentiators/integrators derived through the employment of the aforementioned approximations, is very important factor for achieving high performance approximation of the fractional-order elements. A comparative study of the accuracy offered by the Continued Fraction Expansion and the Oustaloup’s approximation is performed in this paper. As a next step, the corresponding implementations of the emulators of the fractional-order elements, derived using fundamental active cells such as operational amplifiers, operational transconductance amplifiers, current conveyors, and current feedback operational amplifiers realized in commercially available discrete-component IC form, are compared in terms of the most important performance characteristics. The most suitable of them are further compared using the OrCAD PSpice software.

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