scholarly journals Implementation of Clock Gating for Power Optimizing in Synchronous Design

2018 ◽  
Vol 25 (3) ◽  
pp. 12-18
Author(s):  
Hussein Shakor Mogheer ◽  
Khamees Khalaf Hasan
Keyword(s):  
Power Consumption ◽  
Huffman Coding ◽  
Clock Gating ◽  
Verilog Hdl ◽  
Compression Technique ◽  
Design Procedures ◽  
Asic Design ◽  
Quartus Ii ◽  
Typical Cell ◽  
Novel Method

Huffman coding is very important technique in information theory. Compression technique is the technology for reducing the amount of data used to denote any content without decreasing the quality. Furthermore, Clock gating is an effective method for decreasing power consumption in a sequence design. It saves more power by dividing the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. This paper aim to design Huffman coding and decoding process with proposing a novel method of clock gating to achieve low power consumption. Huffman design is executed by expending ASIC design procedures. With the purpose of executing the encoder and decoder structures, 130 nm typical cell technology libraries are utilized for ASIC implementation. The simulations are completed by utilizing Modelsim tool. The design of coding and decoding process has been made using Verilog HDL language. Moreover, it carried out using Quartus II 14.1 Web Edition (64-Bit).

scholarly journals A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer

2018 ◽  
Vol 11 (2) ◽  
pp. 60-66
Author(s):  
Hussein Shakor Moghee
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
New Technology ◽  
Reducing Power ◽  
Digital Design ◽  
Total Power ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Quartus Ii ◽  
State Technique

This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

scholarly journals 64bit Hybrid Adder for ALU Design Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 604-698
Keyword(s):  
Comparative Analysis ◽  
Power Consumption ◽  
Processing Unit ◽  
Central Processing ◽  
Asic Design ◽  
Proposed Model ◽  
Ripple Carry Adder ◽  
Quartus Ii ◽  
Carry Select Adder ◽  
Logic Unit

The Arithmetic Logic Unit is an important component of any Central Processing Unit. An improvement of the speed, area, and power consumption of an ALU directly promotes the performance of the system. Thus, optimization of the ALU design is necessary and for this reason several common adders such as the ripple carry adder, etc. and a proposed model of a 64bit hybrid adder were designed, and a comparative analysis of their performance was studied. The proposed hybrid adder was developed using an 8bit Ripple Carry adder that evaluates the LSB followed by a Carry skip adder block consisting of a 4bit Carry Skip Adder, an 8bit Carry Skip, another 8bit Carry Skip, followed by a 4bit Carry Skip Adder, and finally the MSB is calculated by a 32bit Carry Select Adder. The adders were designed in Verilog on ModelSim-Altera 10.1d (Quartus II 13.0sp1) and later the schematic was obtained on Genus Synthesis (RTL Compiler) of Cadence for ASIC design using 45nm technology. Each adder showed some advantages, but the proposed hybrid adder optimized all aspects of the model while increasing the speed of the device.

scholarly journals A Novel Method for Detecting Abnormal Energy Data in Building Energy Monitoring System

2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Liang Zhao
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Real Time ◽  
Difference Method ◽  
Building Energy ◽  
Energy Monitoring ◽  
Order Difference ◽  
Energy Data ◽  
First Order ◽  
Novel Method

This paper presents a novel abnormal data detecting algorithm based on the first order difference method, which could be used to find out outlier in building energy consumption platform real time. The principle and criterion of methodology are discussed in detail. The results show that outlier in cumulative power consumption could be detected by our method.

Reducing AES power consumption using clock gating

2021 ◽  
Author(s):  
Piotr Chodorowski ◽  
Zbigniew Szaszkowski
Keyword(s):  
Power Consumption ◽  
Clock Gating

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

scholarly journals Lossless text compression using GPT-2 language model and Huffman coding

2021 ◽  
Vol 102 ◽  
pp. 04013
Author(s):  
Md. Atiqur Rahman ◽  
Mohamed Hamada
Keyword(s):  
Data Compression ◽  
State Of The Art ◽  
Language Model ◽  
Huffman Coding ◽  
Original Text ◽  
Text Compression ◽  
Compression Technique ◽  
Daily Life Activities ◽  
Burrows Wheeler Transform ◽  
Compressed Data

Modern daily life activities produced lots of information for the advancement of telecommunication. It is a challenging issue to store them on a digital device or transmit it over the Internet, leading to the necessity for data compression. Thus, research on data compression to solve the issue has become a topic of great interest to researchers. Moreover, the size of compressed data is generally smaller than its original. As a result, data compression saves storage and increases transmission speed. In this article, we propose a text compression technique using GPT-2 language model and Huffman coding. In this proposed method, Burrows-Wheeler transform and a list of keys are used to reduce the original text file’s length. Finally, we apply GPT-2 language mode and then Huffman coding for encoding. This proposed method is compared with the state-of-the-art techniques used for text compression. Finally, we show that the proposed method demonstrates a gain in compression ratio compared to the other state-of-the-art methods.

scholarly journals A Novel Method of Minimizing Power Consumption for Existing Chiller Plant

2017 ◽  
Vol 205 ◽  
pp. 1959-1966 ◽  
Author(s):  
Xue Xue ◽  
Tian Sun ◽  
Wenxing Shi ◽  
Xinhong Li
Keyword(s):  
Power Consumption ◽  
Novel Method

Design of Effective Lossless Data Compression Technique for Multiple Genomic DNA Sequences

2021 ◽  
pp. 17-25
Author(s):  
Mahmud Alosta ◽  
◽  
◽  
Alireza Souri
Keyword(s):  
Data Compression ◽  
Dna Sequences ◽  
Genomic Dna ◽  
Arithmetic Coding ◽  
Huffman Coding ◽  
Compression Technique ◽  
Compression Performance ◽  
Proposed Model ◽  
Evaluation Parameters ◽  
Genome Dataset

In recent years, a massive amount of genomic DNA sequences are being created which leads to the development of new storing and archiving methods. There is a major challenge to process, store or transmit the huge volume of DNA sequences data. To lessen the number of bits needed to store and transmit data, data compression (DC) techniques are proposed. Recently, DC becomes more popular, and large number of techniques is proposed with applications in several domains. In this paper, a lossless compression technique named Arithmetic coding is employed to compress DNA sequences. In order to validate the performance of the proposed model, the artificial genome dataset is used and the results are investigated interms of different evaluation parameters. Experiments were performed on artificial datasets and the compression performance of Arithmetic coding is compared to Huffman coding, LZW coding, and LZMA techniques. From simulation results, it is clear that the Arithmetic coding achieves significantly better compression with a compression ratio of 0.261 at the bit rate of 2.16 bpc.

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