scholarly journals Depletion Layer Modeling for Short Gate Length Non-Uniformly Doped GaAs MESFET Under Dark and Illuminated Condition

2014 ◽  
Vol 1 (1) ◽  
pp. 37-43
Author(s):  
Shweta Tripathi ◽  
S. Jit

This paper presents an analytical expression for the depletion region height of short gate length GaAs MESFET with non-uniform doping profile in the channel region. Both, dark as well as illuminated conditions have been considered for model formulation. Depletion region height sensitivities on the doping parameters have also been demonstrated.

1984 ◽  
Vol 57 (5) ◽  
pp. 665-676
Author(s):  
YEN-CHU WANG ◽  
MAHMOUD BAHRAMI
Keyword(s):  

Author(s):  
Muhammad S Ullah ◽  
Emadelden Fouad ◽  
Xhino M. Domi

The VLSI industry is facing parasitic effects that trouble development in the nanoscale domain. However, instead of replacing the traditional MOSFET design, it would be more advantageous to apply different doping profiles and discerning which deal with specific parasitic effects the best. With a review of Gaussian doping, Uniform doping, and Delta doping profiles and analysis of the FET technology characteristics that use these doping profiles, a comparison can be made among them for integrated circuit design engineers. These doping profiles are compared based on how well they perform against non-ideal and ideal environments. Also, both digital and analog performance are measured to ensure the uniqueness of each doping profile that is present. After getting a list of benefits from each doping profile, it is derived to determine which doping profile works best against a host of parasitic effects and what type of application do these doping profiles have


The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.


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