scholarly journals Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

2019 ◽  
Vol 9 (2S) ◽  
pp. 113-116
Keyword(s):  
High Performance ◽  
Channel Length ◽  
Depletion Region ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
The Past ◽  
Mobility Of Charge Carriers ◽  
Subthreshold Leakage ◽  
Effect Transistor ◽  
Channel Region

The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.

Optimal design of junctionless double gate vertical MOSFET using hybrid Taguchi-GRA with ANN prediction

2019 ◽  
Vol 13 (3) ◽  
pp. 5455-5479
Author(s):  
K. E. Kaharudin ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Random Parameter ◽  
Channel Length ◽  
Influential Factor ◽  
Oxide Semiconductor ◽  
Design Parameters ◽  
Optimized Design ◽  
Double Gate ◽  
Simulation Tools ◽  
Effect Transistor ◽  
Grey Relational

Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (n-JLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (Lch), pillar thickness (Tp), channel doping (Nch) and source/drain doping (Nsd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (ION), off-state current (IOFF), on-off ratio, transconductance (gm), cut-off frequency (fT) and maximum oscillation frequency (fmax), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 106, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively.

scholarly journals Mathematical Modeling and Simulation of Junction less Dual Material Double Gate MOSFET with Various Work Functions

2019 ◽  
Vol 8 (12) ◽  
pp. 3457-3460
Keyword(s):  
Electric Field ◽  
Test System ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Proposed Model ◽  
Effect Transistor ◽  
Work Functions ◽  
Game Plan ◽  
Dual Material

In view of the 2-Dimensional game plan of Poisson's condition, a material science-based model of Double Gate Dual Material Junction less (DGDMJNL) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is made. The advantages of different work capacities connected to the metals in DMDGJNL MOSFET are exhibited and the potential at the inside and qualities of the electric field is uncovered. The proposed model exhibits explicitly demonstrates the effect of the work in electrostatic potential and electric field. It is exhibited that the execution of DMDGJNL MOSFET can be changed by adjusting the channel length extents of control door and shield entryway. The model is assessed by its figured results and those got from a 3D TCAD test system for numerical outcomes.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

A metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length

1990 ◽  
Vol 68 (5) ◽  
pp. 2493-2495 ◽  
Author(s):  
A. Hartstein ◽  
N. F. Albert ◽  
A. A. Bright ◽  
S. B. Kaplan ◽  
B. Robinson ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Length ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
20 Nm

scholarly journals High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 75 ◽  
Author(s):  
Xiaoling Duan ◽  
Jincheng Zhang ◽  
Jiabo Chen ◽  
Tao Zhang ◽  
Jiaduo Zhu ◽  
...  
Keyword(s):  
Energy Band ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Energy Band Structure ◽  
Drain Region ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Silvaco Atlas ◽  
Channel Region

A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

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