scholarly journals A 1 to 10-bit, 85.3 fJ/Conv-step ADC for RFID Sensors

2016 ◽  
Vol 11 (3) ◽  
pp. 177-184
Author(s):  
Marcos Zurita ◽  
Raimundo C. S. Freire ◽  
Smail Tedjini
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Traditional Approach ◽  
Cmos Technology ◽  
Uhf Rfid ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Analog To Digital ◽  
Passive Sensor ◽  
Standard Library

This paper presents the design results of an ultra-low power 1 to 10 bit arbitrary resolution switched capacitor analog to digital converter. In addition to using low-power elements, his project also used a library specifically optimized for the proposed converter rather than a standard library as in traditional approach. This approach enabled the overall converter consumption to be reduced by about 70 %. Consuming 7.29 μA at 1 V supply and taking less than 9 μs per conversion (10 bit mode) it can be used in LF, HF or UHF RFID passive sensor tags. The presented converter was designed in 180 nm CMOS technology occupying about 0.052 mm2 of silicon area. A simulation result shows a figure of merit equal to 85.3 fJ/Conversion-step and 9.5 effective number of bits.

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

2020 ◽  
Vol 17 (1) ◽  
pp. 451-455
Author(s):  
Yahya Mohammed Ali Al-Naamani ◽  
K. Lokesh Krishna ◽  
A. M. Guna Sekhar
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Research Work ◽  
Implantable Devices ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Analog To Digital ◽  
Successive Approximation Register

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

ANALYSIS OF POWER CONSUMPTION SAR-ADC DYNAMIC COMPARATOR

2016 ◽  
Vol 78 (5-9) ◽  
Author(s):  
Julie R. Rusli ◽  
Noor Shelida Salleh ◽  
Masnita M. Isa ◽  
KY Tan ◽  
Suhaidi Shafie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Regeneration Time ◽  
Dynamic Comparators ◽  
Reset Time

Due to the high demand of ultra-low power in digital application, the needs of energy efficient analog-to-digital converter (ADC) are really essential. The comparator being an important part of successive approximation register (SAR)-ADC needs to have optimum performance under low power condition. This paper presents the comparison on power consumption together with the output performance flow power SAR-ADC dynamic comparators from three different design proposed by previous researchers. The three circuits is simulated and compared in terms of power consumption, regeneration time, reset time and output transient.  The simulation is using Cadence Spectre and setup with 0.18µm CMOS technology, VDD at 0.8V and clock speed 2 at MHz.  The analysis results obtained provides the lowest voltage input different (ΔVin) possible for double tail dynamic comparator using 0.18µm CMOS technology while adhering to the 45 corner process requirement.  The results can be used as references for further design of ultra-low power dynamic comparator.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

Transpermanent Magnetics Using Alternating Uniform Linear Stacks

2004 ◽  
Vol 127 (4) ◽  
pp. 679-687
Author(s):  
Larry Silverberg ◽  
Luis Duval
Keyword(s):  
Low Power ◽  
Permanent Magnets ◽  
Traditional Approach ◽  
Reducing Power ◽  
Ultra Low Power ◽  
Flow Rates ◽  
Recent Developments ◽  
Valve Control ◽  
Design And Testing ◽  
Laboratory Prototype

In this paper we apply recent developments in transpermanent magnetics to the problem of ultra-low-power valve control. Whereas the traditional approach to ultra-low-power valve control is based on latching mechanisms that turn off valves during inactive periods, in this paper we describe an approach that eliminates the need for latching mechanisms. Instead of latching mechanisms, the principles of transpermanent magnetics are employed to switch the states of permanent magnets; the use of permanent magnets instead of electromagnets eliminates power loads during inactive periods, thereby reducing power consumption to ultralow levels. The permanent magnets in a transpermanent magnet valve are configured in a stack. The relationships between the strength and number of permanent magnets in the stack and the stroke and resolution of the valve are developed. In this paper we show that the alternating uniform linear stack is well suited for digital process valves having a small number of states. Then in the paper we report on the design and testing of a laboratory prototype valve that uses an alternating uniform linear stack. The prototype valve had five states yielding a range of flow rates between 0 and 1.58m∕s with a resolution of 0.3m∕s. In this paper we find that transpermanent valves represent a promising valve technology for digital process valves.

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