Dendritic Growth Failure of a Mesa Diode

1997 ◽  
Author(s):  
P. Singh ◽  
V. Cozzolino ◽  
G. Galyon ◽  
R. Logan ◽  
K. Troccia ◽  
...  
Keyword(s):  
Electric Fields ◽  
Dendritic Growth ◽  
Silicon Oxide ◽  
Impact Ionization ◽  
Electron Tunneling ◽  
Growth Failure ◽  
Side Wall ◽  
Oxide Interface ◽  
Band Bending ◽  
Cross Section Area

Abstract The time delayed failure of a mesa diode is explained on the basis of dendritic growth on the oxide passivated diode side walls. Lead dendrites nucleated at the p+ side Pb-Sn solder metallization and grew towards the n side metallization. The infinitesimal cross section area of the dendrites was not sufficient to allow them to directly affect the electrical behavior of the high voltage power diodes. However, the electric fields associated with the dendrites caused sharp band bending near the silicon-oxide interface leading to electron tunneling across the band gap at velocities high enough to cause impact ionization and ultimately the avalanche breakdown of the diode. Damage was confined to a narrow path on the diode side wall because of the limited influence of the electric field associated with the dendrite. The paper presents experimental details that led to the discovery of the dendrites. The observed failures are explained in the context of classical semiconductor physics and electrochemistry.

Nitrogen Implantation and Diffusion in Silicon

1999 ◽  
Vol 568 ◽  
Author(s):  
Lahir Shaik Adam ◽  
Mark E. Law ◽  
Omer Dokumaci ◽  
Yaser Haddara ◽  
Cheruvu Murthy ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Gate Oxide ◽  
Nitrogen Diffusion ◽  
Nitrogen Implantation ◽  
Oxide Interface ◽  
Diffusion Behavior ◽  
Czochralski Silicon ◽  
Interface Modeling ◽  
And Diffusion ◽  
Silicon Silicon

ABSTRACTNitrogen implantation can be used to control gate oxide thicknesses [1,2]. This study aims at studying the fundamental behavior of nitrogen diffusion in silicon. Nitrogen at sub-amorphizing doses has been implanted as N2+ at 40 keV and 200 keV into Czochralski silicon wafers. Furnace anneals have been performed at a range of temperatures from 650°C through 1050°C. The resulting annealed profiles show anomalous diffusion behavior. For the 40 keV implants, nitrogen diffuses very rapidly and segregates at the silicon/ silicon-oxide interface. Modeling of this behavior is based on the theory that the diffusion is limited by the time to create a mobile nitrogen interstitial.

Hydrogen passivation of silicon/silicon oxide interface by atomic layer deposited hafnium oxide and impact of silicon oxide underlayer

2018 ◽  
Vol 36 (1) ◽  
pp. 01A116 ◽  
Author(s):  
Evan Oudot ◽  
Mickael Gros-Jean ◽  
Kristell Courouble ◽  
Francois Bertin ◽  
Romain Duru ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Silicon Oxide ◽  
Atomic Layer ◽  
Hydrogen Passivation ◽  
Oxide Interface ◽  
Silicon Silicon

A New Model Silicon/Silicon Oxide Interface Synthesized fromH10Si10O15andSi(100)-2×1

1997 ◽  
Vol 36 (Part 1, No. 3B) ◽  
pp. 1622-1626 ◽  
Author(s):  
K. Z. Zhang ◽  
Leah M. Meeuwenberg ◽  
Mark M. Banaszak Holl ◽  
F. R. McFeely
Keyword(s):  
Silicon Oxide ◽  
Oxide Interface ◽  
New Model ◽  
Silicon Silicon

Impact ionization in semiconductors: Effects of high electric fields and high scattering rates

1992 ◽  
Vol 45 (19) ◽  
pp. 10958-10964 ◽  
Author(s):  
J. Bude ◽  
K. Hess ◽  
G. J. Iafrate
Keyword(s):  
Electric Fields ◽  
Impact Ionization ◽  
High Electric Fields ◽  
Scattering Rates

Impact ionization in AIIIBV semiconductors in high electric fields

1987 ◽  
Vol 140 (1) ◽  
pp. 9-37 ◽  
Author(s):  
A. P. Dmitriev ◽  
M. P. Mikhailova ◽  
I. N. Yassievich
Keyword(s):  
Electric Fields ◽  
Impact Ionization ◽  
High Electric Fields

On the Nature of the Increase in the Electron Mobility in the Inversion Channel at the Silicon–Oxide Interface after the Field Effect

2019 ◽  
Vol 53 (1) ◽  
pp. 85-88 ◽  
Author(s):  
E. I. Goldman ◽  
A. Nabiev ◽  
V. G. Naryshkina ◽  
G. V. Chucheva
Keyword(s):  
Electron Mobility ◽  
Field Effect ◽  
Silicon Oxide ◽  
Oxide Interface ◽  
Inversion Channel

Tem Studies of Silicon-Silicon Oxide Interface Roughness

1987 ◽  
Vol 105 ◽  
Author(s):  
Kyung-Ho Park ◽  
T. Sasaki ◽  
S. Matsuoka ◽  
M. Yoshida ◽  
M. Nakano
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Oxide ◽  
Thermally Grown Oxide ◽  
Interface Roughness ◽  
Silicon On Insulator ◽  
Oxide Surface ◽  
Bulk Single Crystal ◽  
Oxide Interface ◽  
Crystal Silicon ◽  
Cross Sectional

AbstractInterfaces between two kind of substrate, a bulk silicon wafer and a laser-recrystallized Silicon-On-Insulator (SOI), and its thermally grown oxide have been studied. High resolution transmission electron microscopy (HRTEM) of cross sectional specimen shows that the roughness at the interface is atomically flat and nearly uniform for the bulk single crystal silicon and silicon oxide, while being nonuniform and rough as much as 20 nm height for the recrystallized silicon and silicon oxide interface. Consideration of interface between recrystallized silicon and silicon oxide, and the oxide surface above, the observed roughness at the interface is due to original grain boundaries of polycrystalline silicon which was used as the material for the laser recrystallized silicon formation. It is also discussed HRTEM of the interface between polycrystalline silicon and silicon oxide.

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon

2004 ◽  
Vol 810 ◽  
Author(s):  
Nina Burbure ◽  
Kevin S. Jones
Keyword(s):  
Silicon Oxide ◽  
Defect Formation ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Oxide Interface ◽  
Cross Sectional ◽  
Patterned Wafers ◽  
Edge Defects ◽  
Formation And Evolution ◽  
Spike Anneal

ABSTRACTPattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm <100> silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

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