Tem Studies of Silicon-Silicon Oxide Interface Roughness

1987 ◽  
Vol 105 ◽  
Author(s):  
Kyung-Ho Park ◽  
T. Sasaki ◽  
S. Matsuoka ◽  
M. Yoshida ◽  
M. Nakano
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Oxide ◽  
Thermally Grown Oxide ◽  
Interface Roughness ◽  
Silicon On Insulator ◽  
Oxide Surface ◽  
Bulk Single Crystal ◽  
Oxide Interface ◽  
Crystal Silicon ◽  
Cross Sectional

AbstractInterfaces between two kind of substrate, a bulk silicon wafer and a laser-recrystallized Silicon-On-Insulator (SOI), and its thermally grown oxide have been studied. High resolution transmission electron microscopy (HRTEM) of cross sectional specimen shows that the roughness at the interface is atomically flat and nearly uniform for the bulk single crystal silicon and silicon oxide, while being nonuniform and rough as much as 20 nm height for the recrystallized silicon and silicon oxide interface. Consideration of interface between recrystallized silicon and silicon oxide, and the oxide surface above, the observed roughness at the interface is due to original grain boundaries of polycrystalline silicon which was used as the material for the laser recrystallized silicon formation. It is also discussed HRTEM of the interface between polycrystalline silicon and silicon oxide.

scholarly journals Анодное окисление слоев кремний-на-изоляторе, созданных методом водородного переноса

2019 ◽  
Vol 53 (2) ◽  
pp. 253
Author(s):  
И.Е. Тысченко ◽  
И.В. Попов ◽  
Е.В. Спесивцев
Keyword(s):  
Oxidation Rate ◽  
Hydrogen Transfer ◽  
Single Crystal Silicon ◽  
Interatomic Interaction ◽  
Surface Region ◽  
Bound State ◽  
Silicon On Insulator ◽  
Bulk Single Crystal ◽  
Crystal Silicon ◽  
Insulator Layer

AbstractThe anodic oxidation rate of silicon-on-insulator films fabricated by hydrogen transfer is studied as a function of the temperature of subsequent annealing. It is established that the oxidation rate of transferred silicon-on-insulator films is five times lower compared to the oxidation rate of bulk single-crystal silicon samples. The oxidation rate increases, as the annealing temperature is elevated in the range 700–1100°C and as the depth of gradually removed anode-oxidized layers is increased. The results obtained in the study are attributed to an increase in the efficiencies of the anodic current and oxygen–silicon interatomic interaction due to the annealing of defects and due to release of hydrogen from the bound state, respectively. The formation of hydrogen bubbles in the surface region of silicon due to the diffusion of hydrogen, released in the process of the oxidation reaction, towards micropores in the silicon-on-insulator layer is detected.

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon

2004 ◽  
Vol 810 ◽  
Author(s):  
Nina Burbure ◽  
Kevin S. Jones
Keyword(s):  
Silicon Oxide ◽  
Defect Formation ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Oxide Interface ◽  
Cross Sectional ◽  
Patterned Wafers ◽  
Edge Defects ◽  
Formation And Evolution ◽  
Spike Anneal

ABSTRACTPattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm <100> silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

scholarly journals Interface Roughness Effects in Ultra-Thin Tunneling Oxides

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 47-51 ◽  
Author(s):  
D. Z.-Y. Ting ◽  
Erik S. Daniel ◽  
T. C. Mcgill
Keyword(s):  
Silicon Oxide ◽  
Theoretical Study ◽  
Interface Roughness ◽  
Oxide Interface ◽  
Roughness Effects ◽  
Direct Tunneling ◽  
Silicon Based

Advanced MOSFET for ULSI and novel silicon-based devices require the use of ultrathin tunneling oxides where non-uniformity is often present. We report on our theoretical study of how tunneling properties of ultra-thin oxides are affected by roughness at the silicon/oxide interface. The effect of rough interfacial topography is accounted for by using the Planar Supercell Stack Method (PSSM) which can accurately and efficiently compute scattering properties of 3D supercell structures. Our results indicate that while interface roughness effects can be substantial in the direct tunneling regime, they are less important in the Fowler-Nordheim regime.

TEM investigation of the YSZ-on-insulator structure

1995 ◽  
Vol 53 ◽  
pp. 472-473
Author(s):  
D.S. Zhou ◽  
Q.X. Jia ◽  
X.D. Wu ◽  
T.E. Mitchell
Keyword(s):  
Heat Treatment ◽  
Single Crystal ◽  
Semiconductor Device ◽  
Rutherford Backscattering Spectrometry ◽  
Semiconductor Industry ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
Cross Sectional ◽  
Lattice Match

Silicon-on-insulator (SOI) structures have been widely used in the semiconductor industry as substrates to grow various devices. They are usually prepared by a process called separation by implantation of oxygen (SIMOX). As an alternative, single crystal yttria-stabilized-zirconia (YSZ) can be grown on single crystal silicon substrates, followed by heat treatment in oxygen to form an intermediate SiO2 layer. This YSZ-on-silicon structure has the potential to be used as a new SOI material in semiconductor device fabrication.YSZ has a cubic (fluorite type) structure with a lattice parameter of 0.514 ~ 0.523 nm (as compared to 0.543 nm for silicon) depending on its Y2O3 content. The good lattice match between YSZ and silicon makes epitaxial growth possible. In this experiment, the pulsed laser deposition technique has been employed to grow YSZ thin films on single crystal p-Si (100) wafers. Post-deposition heat treatment was carried out at 850°C for 1.5 h in dry oxygen at 1 atmosphere. The structure was first examined by Rutherford backscattering spectrometry and x-ray diffraction, and then by cross-sectional transmission electron microscopy (XTEM) techniques.

XTEM analysis of buried layer structure of silicon-on-insulator materials

1990 ◽  
Vol 48 (4) ◽  
pp. 666-668
Author(s):  
Ni Rushan ◽  
Lin Chenglu
Keyword(s):  
Silicon Nitride ◽  
Single Crystal ◽  
Oxide Layer ◽  
Silicon Oxide ◽  
Single Crystal Silicon ◽  
Silicon On Insulator ◽  
High Dose ◽  
Main Concern ◽  
Crystal Silicon ◽  
Silicon Oxide Layer

It Is well known that a buried silicon nitride or silicon oxide layer in silicon can be formed by high dose >150 KeV nitrogen or oxygen implantation into single crystal silicon followed by high temperature annealing. This is one of the techniques to produce silicon-on-insulator (SOI) structures which is promising for a variety of potential application in VLSI, high-voltage devices, high density CMOS circuits and possibly 3-dimensional integration, etc. The main concern is how to produce a buried dielective layer with good insulating properties and with a high quality single crystal silicon overlayer on it.In this paper the microstructures of buriea silicon nitride and silicon oxide layer of the SOI materials formed by N+ or O+ implantation in single-crystal silicon are studied oy means of cross-sectional transmission electron microscopy (XTEM) and infrared (IR) absorption measurements.

Kinetics and Microstructure of Transiently Annealed Implanted Polycrystalline Silicon Layers

1989 ◽  
Vol 157 ◽  
Author(s):  
J.M.C. England ◽  
P.J. Timans ◽  
R.A. Mcmahon ◽  
H. Ahmed ◽  
C. Hill ◽  
...  
Keyword(s):  
Grain Size ◽  
Polycrystalline Silicon ◽  
Annealing Temperature ◽  
Solid Phase ◽  
Interface Roughness ◽  
Cross Sectional ◽  
Time Resolved ◽  
Microstructural Changes ◽  
Transmission Electron

ABSTRACTMicrostructural changes occurring during the early stages of rapid thermal annealing of polycrystalline silicon bipolar emitters crucially affect the final dopant distribution and hence the performance of these devices. The first stage of annealing is epitaxial regrowth in the solid phase of the layer amorphised by the implantation. In-situ studies using time-resolved reflectivity measurements, combined with cross-sectional transmission electron microscopy of partly annealed structures, have determined the effects of initial grain size, annealing temperature and amorphising species (Si or As) on the rate of regrowth and the microstructural changes which occur during annealing. As the grain size is reduced, the regrowth rate decreases and the interface roughness increases. Arsenic implantation alters the rate of regrowth in such a manner as to produce a smoother interface than that in silicon implanted material.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy

2006 ◽  
Author(s):  
J.S. McMurray ◽  
C.M. Molella
Keyword(s):  
The Body ◽  
Silicon On Insulator ◽  
Back Side ◽  
Cross Sectional ◽  
Plan View ◽  
Spreading Resistance ◽  
Scanning Capacitance Microscopy ◽  
Root Cause ◽  
Cross Sectional Imaging ◽  
Active Channel

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

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