Failure Analysis of Tungsten Stud Defect from the CMP Process

Author(s):  
K. Takagi ◽  
Y. Kohno ◽  
S. Nukii

Abstract This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.

Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.


Author(s):  
H.J. Ryu ◽  
A.B. Shah ◽  
Y. Wang ◽  
W.-H. Chuang ◽  
T. Tong

Abstract When failure analysis is performed on a circuit composed of FinFETs, the degree of defect isolation, in some cases, requires isolation to the fin level inside the problematic FinFET for complete understanding of root cause. This work shows successful application of electron beam alteration of current flow combined with nanoprobing for precise isolation of a defect down to fin level. To understand the mechanism of the leakage, transmission electron microscopy (TEM) slice was made along the leaky drain contact (perpendicular to fin direction) by focused ion beam thinning and lift-out. TEM image shows contact and fin. Stacking fault was found in the body of the silicon fin highlighted by the technique described in this paper.


Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks

Abstract This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.


Author(s):  
Hui Pan ◽  
Thomas Gibson

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.


2018 ◽  
Author(s):  
R. Gunawan ◽  
E. Sugiarti ◽  
Isnaeni ◽  
R. I. Purawiardi ◽  
H. Widodo ◽  
...  

Author(s):  
Liang Hong ◽  
Jia Li ◽  
Haifeng Wang

Abstract This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.


Author(s):  
Steve Wang ◽  
Frederick Duewer ◽  
Shashidar Kamath ◽  
Christopher Kelly ◽  
Alan Lyon ◽  
...  

Abstract Xradia has developed a laboratory table-top transmission x-ray microscope, TXM 54-80, that uses 5.4 keV x-ray radiation to nondestructively image buried submicron structures in integrated circuits with at better than 80 nm 2D resolution. With an integrated tomographic imaging system, a series of x-ray projections through a full IC stack, which may include tens of micrometers of silicon substrate and several layers of Cu interconnects, can be collected and reconstructed to produce a 3D image of the IC structure at 100 nm resolution, thereby allowing the user to detect, localize, and characterize buried defects without having to conduct layer by layer deprocessing and inspection that are typical of conventional destructive failure analysis. In addition to being a powerful tool for both failure analysis and IC process development, the TXM may also facilitate or supplant investigations using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and focused ion beam (FIB) tools, which generally require destructive sample preparation and a vacuum environment.


2016 ◽  
Vol 16 (4) ◽  
pp. 3383-3387 ◽  
Author(s):  
Toichiro Goto ◽  
Nahoko Kasai ◽  
Rick Lu ◽  
Roxana Filip ◽  
Koji Sumitomo

Interfaces between single neurons and conductive substrates were investigated using focused ion beam (FIB) milling and subsequent scanning electron microscopy (SEM) observation. The interfaces play an important role in controlling neuronal growth when we fabricate neuron-nanostructure integrated devices. Cross sectional images of cultivated neurons obtained with an FIB/SEM dual system show the clear affinity of the neurons for the substrates. Very few neurons attached themselves to indium tin oxide (ITO) and this repulsion yielded a wide interspace at the neuron-ITO interface. A neuron-gold interface exhibited partial adhesion. On the other hand, a neuron-titanium interface showed good adhesion and small interspaces were observed. These results are consistent with an assessment made using fluorescence microscopy. We expect the much higher spatial resolution of SEM images to provide us with more detailed information. Our study shows that the interface between a single neuron and a substrate offers useful information as regards improving surface properties and establishing neuron-nanostructure integrated devices.


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