Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing

2008 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
P.K. Tan ◽  
Y.W. Goh ◽  
J.L. Cai ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electronic Devices ◽  
Random Access ◽  
Electrical Characterization ◽  
Electrical Parameters ◽  
Access Memory ◽  
Nanoscale Sram ◽  
Site Identification ◽  
The Impact

Abstract As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.

Electrical Characterization of the Access Transistor of Deep Trench Based DRAM Products via Backside Contacting

2004 ◽  
Author(s):  
Werner Lehner ◽  
Siegfried Pauthner ◽  
Herbert Radeck ◽  
Udo Weber ◽  
Jérôme Touzel
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Electrical Characterization ◽  
Access Memory ◽  
Deep Trench ◽  
Drain Side ◽  
The One ◽  
Basis Structure

Abstract Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.

Single Cell Element of Chalcogenide Random Access Memory Fabricated with the Focused Ion Beam Method

2004 ◽  
Vol 21 (10) ◽  
pp. 2054-2056 ◽  
Author(s):  
Liu Bo ◽  
Song Zhi-Tang ◽  
Feng Song-Lin ◽  
Chen Bomy
Keyword(s):  
Single Cell ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Cell Element ◽  
Beam Method

Semi-Automated Full Wafer In-Line SRAM Failure Analysis by Dual Beam Focused Ion Beam (FIB)

2010 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Harvey E. Berman ◽  
Carmelo F. Scrudato ◽  
Aaron D. Shore ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Static Random Access Memory ◽  
Embedded Memory ◽  
Access Memory ◽  
Chip Design ◽  
Dual Beam ◽  
Image Prior ◽  
Map Data

Abstract The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.

Current-Voltage Characteristic of C-RAM Nano-Cell-Element

2007 ◽  
Vol 121-123 ◽  
pp. 591-594
Author(s):  
Bo Liu ◽  
Zhi Tang Song ◽  
Song Lin Feng ◽  
Bomy Chen
Keyword(s):  
Focused Ion Beam ◽  
Bottom Electrode ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Cell Element ◽  
Current Voltage ◽  
Beam Method ◽  
Current Voltage Characteristics ◽  
Contact Size

Nano-cell-elements of chalcogenide random access memory (C-RAM) based on Ge2Sb2Te5 films have been successively fabricated by using the focused ion beam method. The minimum contact size between the Ge2Sb2Te5 phase change film and bottom electrode film in the nano-cell-element is in diameter of 90nm. The current-voltage characteristics of the C-RAM cell element are studied using the home-made current-voltage tester in our laboratory. The minimum SET current of about 0.3mA is obtained.

Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis

1997 ◽  
Author(s):  
D. Luo ◽  
X. Song
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Operating Life ◽  
New Techniques ◽  
Analysis Techniques ◽  
Temperature Operating ◽  
Voltage Contrast

Abstract A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with Fffi passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Focused Ion Beam Irradiation Induced Damages on CMOS and Bipolar Technologies

1998 ◽  
Author(s):  
J. Benbrik ◽  
G. Rolland ◽  
P. Perdu ◽  
B. Benteo ◽  
M. Casari ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electronic Devices ◽  
Complete Characterization ◽  
Bipolar Transistors ◽  
Ion Beam Irradiation ◽  
Physical Mechanisms ◽  
Dc Characteristics ◽  
Electrical Degradation ◽  
Physical Phenomena

Abstract Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

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