Semi-Automated Full Wafer In-Line SRAM Failure Analysis by Dual Beam Focused Ion Beam (FIB)

2010 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Harvey E. Berman ◽  
Carmelo F. Scrudato ◽  
Aaron D. Shore ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Static Random Access Memory ◽  
Embedded Memory ◽  
Access Memory ◽  
Chip Design ◽  
Dual Beam ◽  
Image Prior ◽  
Map Data

Abstract The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

Single Cell Element of Chalcogenide Random Access Memory Fabricated with the Focused Ion Beam Method

2004 ◽  
Vol 21 (10) ◽  
pp. 2054-2056 ◽  
Author(s):  
Liu Bo ◽  
Song Zhi-Tang ◽  
Feng Song-Lin ◽  
Chen Bomy
Keyword(s):  
Single Cell ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Cell Element ◽  
Beam Method

Electrical Characterization of the Access Transistor of Deep Trench Based DRAM Products via Backside Contacting

2004 ◽  
Author(s):  
Werner Lehner ◽  
Siegfried Pauthner ◽  
Herbert Radeck ◽  
Udo Weber ◽  
Jérôme Touzel
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Electrical Characterization ◽  
Access Memory ◽  
Deep Trench ◽  
Drain Side ◽  
The One ◽  
Basis Structure

Abstract Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.

Current-Voltage Characteristic of C-RAM Nano-Cell-Element

2007 ◽  
Vol 121-123 ◽  
pp. 591-594
Author(s):  
Bo Liu ◽  
Zhi Tang Song ◽  
Song Lin Feng ◽  
Bomy Chen
Keyword(s):  
Focused Ion Beam ◽  
Bottom Electrode ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Cell Element ◽  
Current Voltage ◽  
Beam Method ◽  
Current Voltage Characteristics ◽  
Contact Size

Nano-cell-elements of chalcogenide random access memory (C-RAM) based on Ge2Sb2Te5 films have been successively fabricated by using the focused ion beam method. The minimum contact size between the Ge2Sb2Te5 phase change film and bottom electrode film in the nano-cell-element is in diameter of 90nm. The current-voltage characteristics of the C-RAM cell element are studied using the home-made current-voltage tester in our laboratory. The minimum SET current of about 0.3mA is obtained.

Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis

1997 ◽  
Author(s):  
D. Luo ◽  
X. Song
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Access Memory ◽  
Operating Life ◽  
New Techniques ◽  
Analysis Techniques ◽  
Temperature Operating ◽  
Voltage Contrast

Abstract A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with Fffi passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.

scholarly journals Application of FIB/SEM and TEM to Bit Failure Analyses in SRAM Arrays

2003 ◽  
Vol 782 ◽  
Author(s):  
Wentao Qin ◽  
Alex Volinsky ◽  
Larry Rice ◽  
Lorraine Johnston ◽  
David Theodore
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Embedded Memory ◽  
Area Of Interest ◽  
Microelectronic Devices ◽  
Dual Beam ◽  
Sem Imaging ◽  
Lift Off ◽  
Failure Site

ABSTRACTMany microelectronic chips contain embedded memory arrays. A single SRAM bit-cell contains several transistors. Failure of any of the transistors makes the entire bit-cell inoperable. Dual-beam Focused Ion Beam (FIB) combines the slicing capability of FIB with in-situ SEM imaging. The combination offers unparalleled precision in looking for root causes of failures in microelectronic devices. Once a failure site is located, an FIB lift-off method can be used to prepare a TEM sample containing the area of interest. Further structural, elemental information can then be acquired from the failure site. We report here analyses of single and multiple bit failures in SRAM arrays carried out using FIB/SEM, and in two cases TEM imaging and EDS/PEELS. Root causes of bit failures including remnant seed-layer metal between stacked vias have been identified.

Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing

2008 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
P.K. Tan ◽  
Y.W. Goh ◽  
J.L. Cai ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electronic Devices ◽  
Random Access ◽  
Electrical Characterization ◽  
Electrical Parameters ◽  
Access Memory ◽  
Nanoscale Sram ◽  
Site Identification ◽  
The Impact

Abstract As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.

To Eliminate Curtain Effect of FIB TEM Samples by a Combination of Sample Dicing and Backside Milling

2014 ◽  
Author(s):  
Jian-Shing Luo ◽  
Hsiu Ting Lee
Keyword(s):  
Sample Preparation ◽  
Focused Ion Beam ◽  
Preparation Method ◽  
Low Cost ◽  
Ion Beam ◽  
Sample Preparation Method ◽  
Site Specific ◽  
Dual Beam ◽  
Transmission Electron

Abstract Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

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