Novel Application of the OBIRCh Amplifier for Timing Failure Localization

2008 ◽  
Author(s):  
M. Sienkiewicz ◽  
P. Perdu ◽  
S. Brule ◽  
A. Firiti ◽  
O. Crepel
Keyword(s):  
Failure Analysis ◽  
Mixed Mode ◽  
Flow Time ◽  
Real Case ◽  
Simple Application ◽  
Application Field ◽  
Laser Techniques ◽  
Mapping Techniques ◽  
Failure Localization

Abstract Soft defects localization by laser techniques on dynamically working ICs is widely used for Failure Analysis (FA). In this context, many AC signal-oriented analysis methods have been introduced to date (SDL, LADA…) or are under development (xVM…). Sophisticated tools are available to localize these kinds of failures but not every FA laboratory has them. By fully exploiting the capabilities of static localization tools, it is possible to deal with timing issues. In this paper, we propose a novel application of the OBIRCh amplifier related to the timing issues on a real case study (mixed-mode device). This novel and very simple application makes the analysis flow time-attractive and enlarges the application field of mapping techniques on the existing tools.

Development of Laser-Based Variation Mapping Techniques – Another Way to Increase the Successful Analysis Rate on Analog & Mixed-Mode ICs

2009 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Kevin Sanchez ◽  
Luigi Cattaneo ◽  
Philippe Perdu ◽  
Abdellatif Firiti ◽  
...  
Keyword(s):  
Laser Beam ◽  
Mixed Mode ◽  
Phase Variation ◽  
Added Value ◽  
High Signal ◽  
Classical Dynamic ◽  
Mapping Techniques ◽  
Successful Analysis ◽  
Functional Mode

Abstract The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.

Failure Localization of an Electrical Transient Behavior on a Mixed-Mode IC by Using Static Emission Microscopy Technique

2013 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Estelle Huynh ◽  
Alain Vidal
Keyword(s):  
Mixed Mode ◽  
Transient Behavior ◽  
Microscopy Technique ◽  
Wafer Fab ◽  
Emission Microscopy ◽  
Failure Localization

Abstract This paper presents a case study on reliability reject on a Freescale mixed-mode IC. It focuses on a novel use of one of most frequently used failure localization techniques: static emission microscopy (EMMI) to localize a failure due to an electrical transient behavior. This work helped Freescale to identify a wafer fab process limitation and contributed to test improvement.

Failure Analysis Case Study of a 1.5 Meter Space Flex Harness

2017 ◽  
Author(s):  
Erick Kim ◽  
Kamjou Mansour ◽  
Gil Garteiz ◽  
Javeck Verdugo ◽  
Ryan Ross ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Field Of View ◽  
Area Of Interest ◽  
Air Stream ◽  
Novel Method ◽  
Temperature Controlled ◽  
Non Destructive ◽  
Failure Site

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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