Yield Enhancement Using a Combination of Wafer Level Failure Analysis and Defect Isolation Software: Case Studies

2008 ◽  
Author(s):  
Pierre Simon ◽  
Michel Thétiot ◽  
Bernard Picart ◽  
Cathy Kardach ◽  
Herve Deslandes ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Case Studies ◽  
Thermal Emission ◽  
Yield Enhancement ◽  
Wafer Level ◽  
Software Suite ◽  
Time Resolved ◽  
Defect Isolation ◽  
Emission Microscopy

Abstract Yield enhancement has always been an important topic but even more when processes are moving towards smaller geometries. Today, latest FA flow intends to check wafer quality to monitor production in real-time. The purpose is to adjust any derivation coming from the process as fast as possible. The Atmel-CIMPACA laboratory located in Rousset, France, can do Failure Analysis on wafer, thanks to its wafer prober designed to work on DCG systems equipment and integrated CAD software (Meridian, Emiscope, NEXS software suite). Wafer level yield analysis typically requires long setup and multiple dies analysis. Each of the die can be studied with a set a failure analysis (FA) techniques (photo or thermal) emission microscopy [1], laser stimulation techniques [2] or even dynamic probing using time resolved emission [3],[4] or laser based techniques, for the most common ones [5].

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Failure Analysis Methodology on Resistive Open Defects

2014 ◽  
Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Photon Emission ◽  
Analysis Methodology ◽  
Failure Path ◽  
Open Defect ◽  
Emission Microscopy ◽  
Open Defects ◽  
Logic Array ◽  
Failure Site

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

Defect Isolation Tools Accelerate the Failure Analysis Process

2013 ◽  
Author(s):  
Adam Winterstrom ◽  
Kevin Meehan ◽  
Ralph Sanchez ◽  
Rich Ackerman
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Lead Time ◽  
Functional Test ◽  
Diagnostic Process ◽  
Successful Completion ◽  
Root Cause ◽  
Analysis Process ◽  
Scan Test ◽  
Defect Isolation

Abstract This paper presents case studies that highlight the use of novel scan technologies and techniques to quickly test, diagnose, localize, and isolate the root cause of the defects, demonstrating that the solution meets the rapid and constant changing demands of industry. Cases include a device that has seemingly passed the functional test, but not the scan test with emission; a device with emission requiring resolution to its location; and a device having a timing issue that does not have emission. All case studies concluded with successful completion of finding the root cause of the defect. The diagnosis time for each of the three devices was within a period of one to three days per device. The confirmation stage of the defect is the longest lead time of the diagnostic process.

FASTKIT—A Software Tool for Easy Design Visibility and Diagnostic Enhancement for Failure Analysis

2015 ◽  
Author(s):  
Etienne Auvray ◽  
Paul Armagnat
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Software Tool ◽  
Measure Data ◽  
Software Suite ◽  
Laboratory Environment ◽  
Design Database ◽  
Analytical Tools

Abstract The present work is relative to a new software suite that features design comprehension and analogic/logic tracing capability with ease of setup in FA laboratory environment. It also expands and correlates FA measure data to design functionality. With this visibility enhanced environment, we show that FA process can be performed more efficiently. Up to now, very few systems have been built with aim to cover advanced diagnosis setup and real-time navigation with synchronized simulation. We address a general FA software tool which purpose is to automate the design database setup and provide to FA engineer capability to launch reading of all design database including capability of generating new patterns compatible with analytical tools. Based on the flow, we propose a series of tools that will allow the FA engineer to work efficiently.

Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission

2019 ◽  
Author(s):  
Paul Hubert P. Llamera ◽  
Camille Joyce G. Garcia-Awitan
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Near Infrared ◽  
Thermal Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
Distinct Advantage ◽  
Infra Red ◽  
Emission Microscopy ◽  
Lock In

Abstract Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

Case Studies on Application of 3D Real Time X-ray for Flip Chip C4 Package

2014 ◽  
Author(s):  
Lihong Cao ◽  
Wallace Donna ◽  
Loc Tran ◽  
Lynda Tuttle
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Case Studies ◽  
Flip Chip ◽  
X Ray

Abstract This article describes how 3D Real Time X-Ray (RTX) technique enhances the capability of package-level failure analysis of a flip-chip package. 3D RTX was successful in detecting different failure signatures. This paper outlines detailed applications of 3D RTX with case studies.

High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens

2003 ◽  
Author(s):  
S. Thorne ◽  
S. Ippolito ◽  
M. Eraslan ◽  
B. Goldberg ◽  
M.S. Ünlü ◽  
...  
Keyword(s):  
High Resolution ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Visual Inspection ◽  
Thermal Emission ◽  
Numerical Aperture ◽  
Specific Component ◽  
Feature Size ◽  
Analytical Technique ◽  
Emission Microscopy

Abstract As the feature size in integrated circuits (ICs) become smaller, the techniques we use to localize defects must also progress to the level that they can resolve potential errors. Additionally, because most errors cannot be identified by visual inspection alone, it is necessary to develop techniques, such as thermography, with the capability of localizing failures to the specific component or defect at fault. This paper will review the theory and application of an advanced subsurface (through the substrate) analytical technique for IC failure analysis – solid immersion lens thermal emission microscopy.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

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