Case Studies on Application of 3D Real Time X-ray for Flip Chip C4 Package

2014 ◽  
Author(s):  
Lihong Cao ◽  
Wallace Donna ◽  
Loc Tran ◽  
Lynda Tuttle
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Case Studies ◽  
Flip Chip ◽  
X Ray

Abstract This article describes how 3D Real Time X-Ray (RTX) technique enhances the capability of package-level failure analysis of a flip-chip package. 3D RTX was successful in detecting different failure signatures. This paper outlines detailed applications of 3D RTX with case studies.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

Applications of 3D X-Ray Microscopy for Advanced Package Development

2011 ◽  
Vol 2011 (1) ◽  
pp. 001078-001083 ◽  
Author(s):  
K. Fahey ◽  
R. Estrada ◽  
L. Mirkarimi ◽  
R. Katkar ◽  
D. Buckminster ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Development Stage ◽  
Development Effort ◽  
X Ray ◽  
Structural Details ◽  
Volumetric Images ◽  
Advanced Packaging ◽  
Solder Fatigue ◽  
Non Destructive

This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort. Identifying and locating failures embedded deep inside the package, such as a solder fatigue failure within a flip chip package, without the need for physical cross-sectioning is of substantial benefit because it preserves the package for further analysis. Also of utility is the ability to reveal the structural details of the package while producing superior quality 2D and volumetric images. The technique could be used not only for analysis of defects and failures, but also to characterize geometries and morphologies during the process and package development stage.

Lock-in Thermography for Flip-Chip Package Failure Analysis

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Jeffery Huynh ◽  
Joseph Tan ◽  
Meng-Yeow Tay ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Flip Chip ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Lock In

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool

2000 ◽  
Author(s):  
Damion T. Searls ◽  
Anura Don ◽  
Emilie Dy ◽  
Deepak Goyal
Keyword(s):  
Failure Analysis ◽  
Time Domain ◽  
Flip Chip ◽  
Low Voltage ◽  
Time Domain Reflectometry ◽  
Stress Tests ◽  
X Ray ◽  
Customer Returns ◽  
Failure Location ◽  
Electrical Connectivity

Abstract Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

The Application of Two-Dimensional X-ray Hot Stage in Flip Chip Package Failure Analysis

2011 ◽  
Vol 11 (1) ◽  
pp. 141-147 ◽  
Author(s):  
Yan Li ◽  
Rahul Panat ◽  
Bin Li ◽  
Rose Mulligan ◽  
Purushotham Kaushik Muthur Srinath ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Two Dimensional ◽  
X Ray

Yield Enhancement Using a Combination of Wafer Level Failure Analysis and Defect Isolation Software: Case Studies

2008 ◽  
Author(s):  
Pierre Simon ◽  
Michel Thétiot ◽  
Bernard Picart ◽  
Cathy Kardach ◽  
Herve Deslandes ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Case Studies ◽  
Thermal Emission ◽  
Yield Enhancement ◽  
Wafer Level ◽  
Software Suite ◽  
Time Resolved ◽  
Defect Isolation ◽  
Emission Microscopy

Abstract Yield enhancement has always been an important topic but even more when processes are moving towards smaller geometries. Today, latest FA flow intends to check wafer quality to monitor production in real-time. The purpose is to adjust any derivation coming from the process as fast as possible. The Atmel-CIMPACA laboratory located in Rousset, France, can do Failure Analysis on wafer, thanks to its wafer prober designed to work on DCG systems equipment and integrated CAD software (Meridian, Emiscope, NEXS software suite). Wafer level yield analysis typically requires long setup and multiple dies analysis. Each of the die can be studied with a set a failure analysis (FA) techniques (photo or thermal) emission microscopy [1], laser stimulation techniques [2] or even dynamic probing using time resolved emission [3],[4] or laser based techniques, for the most common ones [5].

TDR Analysis of Advanced Microprocessors

2001 ◽  
Author(s):  
David Bethke ◽  
Wayland Seifert
Keyword(s):  
Failure Analysis ◽  
Time Domain ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Signal Amplitude ◽  
Physical Analysis ◽  
X Ray ◽  
Digital Oscilloscope ◽  
Analytical Technique ◽  
The Time Domain

Abstract Time Domain Reflectrometry or TDR is an analytical technique used to determine the impedance and electrical length of conductors. This relatively inexpensive technique utilizes a pulse card and digital oscilloscope whereby the reflected signal amplitude from an initiating pulse is measured versus time. The technique is useful for characterizing the impedance of a conductor in the time domain, and has traditionally been employed in board level analysis. More recently, TDR has been shown to be useful in electrically isolating integrated circuit package failures1. Historically, open failures on non-flip chip devices were resolved through relatively straight-forward, low risk methods in a failure analysis lab. Typically, root cause analysis involved simple verification on a curve tracer, non-destructive inspection using X-Ray imaging, chemical, thermal or mechanical decapsulation, optical and electron microscopy and as necessary, the use of mechanical probe isolation. The implementation of advanced flip chip package technology rendered the traditional isolation methodologies inadequate. After verification and X-ray inspection, a decision had to be made prior to subsequent destructive physical analysis as to the most probable failure location. Since the board interconnects, board interposer, and bump locations were not geometrically aligned, isolation of opens through physical cross-sectioning became risky, tedious and lengthy. These constraints were overcome through the use of TDR analysis. The authors have successfully incorporated the TDR technique into AMD’s microprocessor failure analysis flow, improving success rate, reducing risk and decreasing turn-around time. The paper will include a brief description of TDR theory and hardware, technical barriers that the authors encountered during implementation, sample preparation as well as details where the technique was successfully employed in failure isolation. The remaining portion of this paper provides illustrative examples where TDR was effectively utilized in the analysis of slot A cards, ceramic flip chip PGA pins, and internal package trace failures.

Sign in / Sign up

Export Citation Format

Share Document