Diamond Probe Applications for Nanoprobing

Author(s):  
Sweta Pendyala ◽  
Andrew Dalton ◽  
Sean Zumwalt ◽  
John Miller

Abstract As technology continues to scale down, semiconductor devices and circuitry have become more complex. The layouts are more integrated and the devices do not isolate at contact level like they used to. Due to this, nanoprobing cannot always localize the defect to one gate finger and as a result the follow-on physical analysis gets more complicated and time consuming. In this paper, we will explore an approach to simplify a given circuit and localize the failing finger in that circuit by cutting metal lines using diamond nano-probes [1] on the FEI Hyperion Atomic Force Probe (AFP) Platform. We will also describe some of the other applications of diamond nano-probes in facilitating semiconductor failure analysis.

Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.


2004 ◽  
Vol 811 ◽  
Author(s):  
J. Pétry ◽  
W. Vandervorst ◽  
O. Richard ◽  
T. Conard ◽  
P. DeWolf ◽  
...  

ABSTRACTIn the path to the introduction of high-k dielectric into IC components, a large number of challenges have still to be solved. Some of the major issues concern the low mobility of carriers and the reliability of the devices. Trapped charges in the stack have been identified as being the cause of these issues. With this in mind, we used Conducting Atomic Force Microscopy, combined with physical analysis to understand the nature of these charges. In this contribution, we have studied the uniformity of thin HfO2 layers, with and without anneal. The Conducting Atomic Force microscopy measurements show spots of higher conductivity. Recording local IV's in those ‘weak’ spots suggests that they consist of positive charge. On the other hand, XPS and ToFSIMS analysis show a diffusion of the interfacial SiO2 upwards into the high-k layer. Finally, the comparison of samples with differing high-k material and crystallinity indicates a strong correlation between the weak spots and the presence of silicon in the film.


2021 ◽  
Author(s):  
Randal Mulder

Abstract A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action. An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location. This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.


Author(s):  
Xiang-Dong Wang ◽  
Arnold Yazzie ◽  
John Buchert ◽  
Laurel Will ◽  
Ping Wang ◽  
...  

Abstract Embedded non-volatile memory (NVM) technologies are used in almost all areas of semiconductor chip applications, as it becomes increasingly vital to retain information when the electronics power is off. Nano-probing techniques, such as atomic force probe (AFP), allow us to access individual devices at contact or via levels and characterize the details as much as possible before a decision can be made for physical analysis. This paper reports the application of AFP to characterize each individual bit at contact level or individual column at via1 level. It presents two cases to identify the failures encountered in fabricated embedded NVM: column-column leakage and single bit erase failure. The first case shows that silicide residual could cause column to column leakage by creating electrical path between active areas of adjacent columns, while the second case shows that single bit failures due to low erase current can be recovered with repeated program/erase cycle.


Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.


Author(s):  
Oliver D. Patterson ◽  
Deborah A. Ryan ◽  
Xiaohu Tang ◽  
Shuen Cheng Lei

Abstract In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.


Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.


Author(s):  
Liang-Feng Wen ◽  
Chien-Hui Chen ◽  
Allen Timothy Chang

Abstract This paper presents a method of using a conductive atomic force microscope (C-AFM) to characterize a submicron metal fuse that has been blown open inadequately by laser. In order to obtain a proper I-V curve measured using the C-AFM without affecting the incompletely opened fuse, the paper proposes a method of preserving the fuse by coating its surface with spin-on glass. The paper explains how differences in laser cutting machines resulted in the high failure repair rate of customer product despite equivalent energy and spot size settings. Analysis of the fuse bank circuitry on wafers helped to find the critical physical differences between a fully blown and a poorly blown fuse. By overcoming difficulties in preserving the blown fuse failure sites for C-AFM measurement, laser settings could be easily optimized to ensure proper fuse opening.


Author(s):  
Chuan Zhang ◽  
Yinzhe Ma ◽  
Gregory Dabney ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen

Abstract Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.


Author(s):  
Keith Harber ◽  
Steve Brockett

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.


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