Symptom or Cause? A Case Study

2015 ◽  
Author(s):  
Anuradha Swaminathan ◽  
Joy Liao ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Analysis Data ◽  
Continuous Wave Laser ◽  
Electrical Failure ◽  
Root Cause ◽  
First Case ◽  
Successful Analysis ◽  
28 Nm

Abstract Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.

Scan-Shift Debug Using LVI Phase Mapping

2013 ◽  
Author(s):  
Yin (Roy) S. Ng ◽  
Howard Marks ◽  
Christopher Nemirov ◽  
Chun-Cheng Tsao ◽  
Jim Vickers
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Continuous Wave Laser ◽  
Success Rates ◽  
Established Method ◽  
Electrical Failure ◽  
Voltage Imaging ◽  
Integrity Tests ◽  
Scan Chain ◽  
Domain Information

Abstract Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Case Study—Failure Analysis of a Multiplexer

2016 ◽  
Author(s):  
Michael Woo ◽  
Marcos Campos ◽  
Luigi Aranda
Keyword(s):  
Failure Analysis ◽  
High Reliability ◽  
Component Failure ◽  
Root Cause ◽  
Knowing That ◽  
Cause Of Failure ◽  
The Cost

Abstract A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2020 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Subsea Gas Well Late Life Restart Lesson Learned: Failure Analysis and Operating Strategy

2021 ◽  
Author(s):  
Song Wang ◽  
Lawrence Khin Leong Lau ◽  
Wu Jun Tong ◽  
Kun An ◽  
Jiang Nan Duan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Late Life ◽  
Flow Assurance ◽  
Gas Well ◽  
Subsea Pipeline ◽  
Operating Strategy ◽  
Root Cause ◽  
Financial Impacts ◽  
Transient Multiphase Flow

Abstract This paper elucidates the importance of flow assurance transient multiphase modelling to ensure uninterrupted late life productions. This is discussed in details through the case study of shut-in and restart scenarios of a subsea gas well (namely Well A) located in South China Sea region. There were two wells (Well A and Well B) producing steadily prior to asset shut-in, as a requirement for subsea pipeline maintenance works. However, it was found that Well A failed to restart while Well B successfully resumed production after the pipeline maintenance works. Flow assurance team is called in order to understand the root cause of the failed re-start of Well A to avoid similar failure for Well B and other wells in this region. Through failure analysis of Well A, key root cause is identified and associated operating strategy is proposed for use for Well B, which is producing through the same subsea infrastructure. Transient multiphase flow assurance model including subsea Well A, subsea Well B, associated spools, subsea pipeline and subsea riser is developed and fully benchmarked against field data to ensure realistic thermohydraulics representations of the actual asset. Simulation result shows failed restart of Well A and successful restart of Well B, which fully matched with field observations. Further analysis reveals that liquid column accumulated within the wellbore of Well A associates with extra hydrostatic head which caused failed well restart. Through a series of sensitivity analysis, the possibility of successful Well A restart is investigated by manipulating topsides back pressure settings and production flowrates prior to shut-in. These serve as a methodology to systematically analyze such transient scenario and to provide basis for field operating strategy. The analysis and strategy proposed through detailed modelling and simulation serves as valuable guidance for Well B, should shut-in and restart operation is required. This study shows the importance of modelling prior to late life field operations, in order to avoid similar failed well restart, which causes significant production and financial impacts.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage

2014 ◽  
Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Root Cause Analysis ◽  
Wafer Surface ◽  
Tem Analysis ◽  
Cause Analysis ◽  
Root Cause

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.

Understanding the Cu Void Formation by TEM Failure Analysis

2014 ◽  
Author(s):  
Binghai Liu ◽  
Jie Zhu ◽  
Changqing Chen ◽  
Eddie Er ◽  
Siping Zhao ◽  
...  
Keyword(s):  
Electron Diffraction ◽  
Failure Analysis ◽  
Seed Layer ◽  
Void Formation ◽  
Surface Oxidation ◽  
Alkaline Condition ◽  
Electron Diffraction Analysis ◽  
Root Cause ◽  
Cu Cmp

Abstract In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

A Study of SRAM Device Soft Failures Caused by Contact Volcano Defects Using Nanoprobing Analysis

2011 ◽  
Author(s):  
Yu Hsiang Shu ◽  
Vincent Huang ◽  
Chia Hsing Chao
Keyword(s):  
Failure Analysis ◽  
High Resistance ◽  
Ion Beam ◽  
Analysis Method ◽  
Root Cause ◽  
Parametric Data ◽  
Transmission Electron ◽  
Focus Ion Beam ◽  
Electrical Data

Abstract Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.

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