Scan-Shift Debug Using LVI Phase Mapping

2013 ◽  
Author(s):  
Yin (Roy) S. Ng ◽  
Howard Marks ◽  
Christopher Nemirov ◽  
Chun-Cheng Tsao ◽  
Jim Vickers
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Continuous Wave Laser ◽  
Success Rates ◽  
Established Method ◽  
Electrical Failure ◽  
Voltage Imaging ◽  
Integrity Tests ◽  
Scan Chain ◽  
Domain Information

Abstract Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Symptom or Cause? A Case Study

2015 ◽  
Author(s):  
Anuradha Swaminathan ◽  
Joy Liao ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Analysis Data ◽  
Continuous Wave Laser ◽  
Electrical Failure ◽  
Root Cause ◽  
First Case ◽  
Successful Analysis ◽  
28 Nm

Abstract Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.

Scan chain failure analysis using laser voltage imaging

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1422-1426 ◽  
Author(s):  
Joy Y. Liao ◽  
Steven Kasapi ◽  
Bruce Cory ◽  
Howard Lee Marks ◽  
Yin S. Ng
Keyword(s):  
Failure Analysis ◽  
Voltage Imaging ◽  
Scan Chain

MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing

2019 ◽  
Author(s):  
Jessica Yang ◽  
Omprakash Rengaraj ◽  
Puneet Gupta ◽  
Rudolf Schlangen
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Random Access ◽  
Random Access Memory ◽  
Fault Isolation ◽  
Static Random Access Memory ◽  
Production Testing ◽  
Access Memory ◽  
Electrical Failure ◽  
Voltage Imaging

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing

2011 ◽  
Author(s):  
Steven Kasapi ◽  
William Lo ◽  
Joy Liao ◽  
Bruce Cory ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Wafer Level ◽  
Root Cause ◽  
Non Invasive ◽  
Laser Probing ◽  
Volume Yield ◽  
Scan Chain ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Improved Electrical Failure Analysis/Fault Isolation Tool Development on Server Motherboard Platforms Based on Historic Failure Modes

2004 ◽  
Author(s):  
Patrick G. Opdahl
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Resource Constraints ◽  
Analysis Data ◽  
Fault Isolation ◽  
Tool Development ◽  
Success Rates ◽  
Complete Coverage ◽  
Electrical Failure ◽  
Silicon Devices

Abstract Electrical fault isolation constitutes the first steps in characterizing and isolating the failure modes and root causes of a failing motherboard. Ideally the Failure Analysis Test tools provide complete coverage of all motherboard buses and silicon devices. Time and resource constraints for tool development prevent complete coverage, however, so the challenge is to provide the highest level of debug test coverage in the shortest development schedule. A simplified Fault Isolation process has been created based on historical failure analysis data to reduce the development time and resources to create tools which allow diagnosing failure root causes on high-end server motherboards. This strategy prioritizes the most common types of electrical failure modes and the types of Electrical Failure Analysis / Fault Isolation (EFA-FI) tools best suited to diagnose these modes. The benefits of this strategy include shorter EFA-FI development times, equivalent success rates in failure root cause, lower costs, and more effective EFA-FI tools that can be used within the Design Team and at either OEM or Contract Manufacturing sites.

1848: Revolix 70 Watt 2 Micron Continuous Wave Laser Vaporesection of the Prostate. Preliminary Results After a One Year Follow-Up

2007 ◽  
Vol 177 (4S) ◽  
pp. 614-614
Author(s):  
Thorsten Bach ◽  
Thomas R.W. Herrmann ◽  
Roman Ganzer ◽  
Andreas J. Gross
Keyword(s):  
Continuous Wave ◽  
Continuous Wave Laser ◽  
Preliminary Results ◽  
Wave Laser ◽  
One Year

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

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