Subsea Gas Well Late Life Restart Lesson Learned: Failure Analysis and Operating Strategy

2021 ◽  
Author(s):  
Song Wang ◽  
Lawrence Khin Leong Lau ◽  
Wu Jun Tong ◽  
Kun An ◽  
Jiang Nan Duan ◽  
...  

Abstract This paper elucidates the importance of flow assurance transient multiphase modelling to ensure uninterrupted late life productions. This is discussed in details through the case study of shut-in and restart scenarios of a subsea gas well (namely Well A) located in South China Sea region. There were two wells (Well A and Well B) producing steadily prior to asset shut-in, as a requirement for subsea pipeline maintenance works. However, it was found that Well A failed to restart while Well B successfully resumed production after the pipeline maintenance works. Flow assurance team is called in order to understand the root cause of the failed re-start of Well A to avoid similar failure for Well B and other wells in this region. Through failure analysis of Well A, key root cause is identified and associated operating strategy is proposed for use for Well B, which is producing through the same subsea infrastructure. Transient multiphase flow assurance model including subsea Well A, subsea Well B, associated spools, subsea pipeline and subsea riser is developed and fully benchmarked against field data to ensure realistic thermohydraulics representations of the actual asset. Simulation result shows failed restart of Well A and successful restart of Well B, which fully matched with field observations. Further analysis reveals that liquid column accumulated within the wellbore of Well A associates with extra hydrostatic head which caused failed well restart. Through a series of sensitivity analysis, the possibility of successful Well A restart is investigated by manipulating topsides back pressure settings and production flowrates prior to shut-in. These serve as a methodology to systematically analyze such transient scenario and to provide basis for field operating strategy. The analysis and strategy proposed through detailed modelling and simulation serves as valuable guidance for Well B, should shut-in and restart operation is required. This study shows the importance of modelling prior to late life field operations, in order to avoid similar failed well restart, which causes significant production and financial impacts.

Author(s):  
Michael Woo ◽  
Marcos Campos ◽  
Luigi Aranda

Abstract A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.


Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.


Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.


Author(s):  
Binghai Liu ◽  
Jie Zhu ◽  
Changqing Chen ◽  
Eddie Er ◽  
Siping Zhao ◽  
...  

Abstract In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.


Author(s):  
Yu Hsiang Shu ◽  
Vincent Huang ◽  
Chia Hsing Chao

Abstract Using nanoprobing techniques to accomplish transistor parametric data has been reported as a method of failure analysis in nanometer scale defect. In this paper, we focus on how to identify the influence of Contact high resistance on device soft failures using nanoprobing analysis, and showing that the equivalent mathematical models could be used to describe the corresponding electrical data in a device with Contact high resistance issue. A case study was presented to verify that Contact volcano defect caused Contact high resistance issue, and this issue can be identified via physical failure analysis (PFA) method (e.g. Transmission Electron Microscope and Focus Ion Beam techniques) and nanoprobing analysis method. Finally, we would explain the physical root cause of Contact volcano issue.


Author(s):  
Hei-Ruey Harry Jen ◽  
Gerald S. D’Urso ◽  
Harold Andrews

Abstract When a failure analysis (FA) involves a multiple layer structure separated by a polymeric material such as Benzocyclobutene (BCB), in a plastic package, it becomes a very challenging task to find out where the failure site is and how it failed. This is due to the fact that the chemical de-processing procedure removes BCB as well as the plastic molding compound. This paper outlines the studies carried out to determine the failure site and the root cause of the failure mechanism in a multilayer circuit and the steps taken to fix the problems. The methodology and results of this study are applicable to many other types of circuits.


Author(s):  
Anuradha Swaminathan ◽  
Joy Liao ◽  
Howard Marks

Abstract Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.


2015 ◽  
Author(s):  
Spencer E. Scolnick ◽  
Jonathan C. Garrett ◽  
Steven L. Griffith ◽  
Kevin K. Ward

Author(s):  
Jose Z. Garcia ◽  
Kris Dickson

Abstract This paper describes how a DDR loopback test failure was analyzed successfully after being repackaged from an MBGA into a TBGA package substrate. DDR loopback test methodology is discussed as well as the advanced failure analysis techniques that were used to identify the root cause of failure.


Author(s):  
Peter Jacob

Abstract Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.


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