Enhanced Static Fault Localization Methodology on Resistive Open Defects Using Photon Emission Microscopy and Layout Defect Prediction

2016 ◽  
Author(s):  
A.C.T. Quah ◽  
D. Nagalingam ◽  
G.B. Ang ◽  
C.Q. Chen ◽  
H.H. Ma ◽  
...  
Keyword(s):  
Logic Gate ◽  
Photon Emission ◽  
Floating Gate ◽  
Advanced Technology ◽  
Great Success ◽  
Failure Path ◽  
Novel Method ◽  
Open Defect ◽  
Open Defects ◽  
Technology Nodes

Abstract In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

Failure Analysis Methodology on Resistive Open Defects

2014 ◽  
Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Photon Emission ◽  
Analysis Methodology ◽  
Failure Path ◽  
Open Defect ◽  
Emission Microscopy ◽  
Open Defects ◽  
Logic Array ◽  
Failure Site

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation

2016 ◽  
Author(s):  
Ramya Yeluri ◽  
Ravishankar Thirugnanasambandam ◽  
Cameron Wagner ◽  
Jonathan Urtecho ◽  
Jan M. Neirynck
Keyword(s):  
Duty Cycle ◽  
Thermal Effects ◽  
Second Harmonic ◽  
Fault Isolation ◽  
Advanced Technology ◽  
Temperature Dependent ◽  
First Case ◽  
Improve Accuracy ◽  
Degradation Monitoring ◽  
Technology Nodes

Abstract Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

Advanced technology nodes, a foundry perspective

2012 ◽  
Author(s):  
Jürgen Faul ◽  
Jan Hoentschel ◽  
Maciej Wiatr ◽  
Manfred Horstmann
Keyword(s):  
Advanced Technology ◽  
Technology Nodes

Electromigration Improvement for Advanced Technology Nodes

2019 ◽  
Vol 18 (1) ◽  
pp. 269-274
Author(s):  
Hui-Jung Wu ◽  
Wen Wu ◽  
Roey Shaviv ◽  
Mandy Sriram ◽  
Anshu Pradhan ◽  
...  
Keyword(s):  
Advanced Technology ◽  
Technology Nodes

NCFET: Opportunities & challenges for advanced technology nodes

2017 ◽  
Author(s):  
Zoran Krivokapic ◽  
Ahmedullah Aziz ◽  
Da Song ◽  
Uzma Rana ◽  
Rohit Galatage ◽  
...  
Keyword(s):  
Advanced Technology ◽  
Technology Nodes

The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000001-000005 ◽  
Author(s):  
R. Beica ◽  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
J. Azemar
Keyword(s):  
Semiconductor Industry ◽  
Cost Effective ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Current Trends ◽  
Advanced Packaging ◽  
Scaling Process ◽  
Market Trends ◽  
The Cost ◽  
Technology Nodes

The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package. This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.

Multi-Cell Soft Errors at Advanced Technology Nodes

2015 ◽  
Vol 62 (6) ◽  
pp. 2585-2591 ◽  
Author(s):  
B. L. Bhuva ◽  
N. Tam ◽  
L. W. Massengill ◽  
D. Ball ◽  
I. Chatterjee ◽  
...  
Keyword(s):  
Soft Errors ◽  
Advanced Technology ◽  
Technology Nodes

Electron beam metrology for advanced technology nodes

2019 ◽  
Vol 58 (SD) ◽  
pp. SD0801 ◽  
Author(s):  
Gian Francesco Lorusso ◽  
Naoto Horiguchi ◽  
Jürgen Bömmels ◽  
Christopher J. Wilson ◽  
Geert Van den bosch ◽  
...  
Keyword(s):  
Electron Beam ◽  
Advanced Technology ◽  
Technology Nodes
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