Short Wavelength Probing for Fault Isolation Applications

2020 ◽  
Author(s):  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Vasanth Somasundaram ◽  
Phoa Angeline ◽  
Pey Kin Leong ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Spatial Resolution ◽  
Short Wavelength ◽  
Fault Isolation ◽  
Laser Probing ◽  
Successful Case ◽  
20 Nm

Abstract Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

Laser Voltage Imaging: A New Perspective of Laser Voltage Probing

2010 ◽  
Author(s):  
Yin S. Ng ◽  
Ted Lundquist ◽  
Dmitry Skvortsov ◽  
Joy Liao ◽  
Steven Kasapi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Functional Failure ◽  
Voltage Imaging ◽  
Laser Probing ◽  
New Perspective

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Case Study Failure Analysis of an Ultra-High Vacuum Enclosure Made of a Silicon Chip and Borosilicate Glass for the Cold Atom Laboratory

2017 ◽  
Author(s):  
Gil Garteiz ◽  
Javeck Verdugo ◽  
David Aveline ◽  
Eric Williams ◽  
Arvid Croonquist ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Borosilicate Glass ◽  
High Vacuum ◽  
Cold Atom ◽  
Fault Isolation ◽  
Ultra High Vacuum ◽  
Liquid Bath

Abstract In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.

Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices

2004 ◽  
Author(s):  
Dat Nguyen ◽  
Thao To ◽  
Ray Harrison ◽  
Cuong Phan ◽  
John Drummond
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Front Side ◽  
Defect Identification ◽  
Automated Test Equipment ◽  
Special Analysis ◽  
Failure Correlation ◽  
Similar Sample

Abstract Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

New Techniques for Logic Fault Diagnosis with a Case Study on the 440BX Chipset

1999 ◽  
Author(s):  
Srikanth Venkataraman ◽  
Scott B. Drummonds
Keyword(s):  
Fault Diagnosis ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Automated Diagnosis ◽  
New Techniques ◽  
Design And Manufacturing ◽  
Cause Of Failure

Abstract Logic fault diagnosis or fault isolation is the process of analyzing failing random logic portions of a chip to isolate the cause of failure. Fault diagnosis or fault isolation (FI) plays an important role in multiple applications at different stages of design and manufacturing. Most currently deployed FI techniques for random logic fault isolation include physical techniques with limited automated diagnosis followed by e-beam and/or laser voltage probing (LVP) on packaged parts. This paper will present the methodology and FI results obtained by executing automated scan based diagnosis on a chipset product (440BX). The logic diagnosis techniques used are presented along with simulation and Failure Analysis (FA) results

Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement

2004 ◽  
Author(s):  
Chia Ling Kong ◽  
Mohammed R. Islam
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Low Voltage ◽  
Circuit Simulation ◽  
Physical Structure ◽  
Fault Isolation ◽  
Embedded Memory ◽  
Yield Improvement ◽  
Multi Level

Abstract Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Fault isolation in a case study of failure analysis on Metal–Insulator–Metal capacitor structures

2015 ◽  
Vol 55 (9-10) ◽  
pp. 1640-1643 ◽  
Author(s):  
V. Giuffrida ◽  
P. Barbarino ◽  
G. Muni ◽  
G. Calvagno ◽  
G. Latteo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Metal Insulator ◽  
Metal Insulator Metal

Stacked Polysilicon/Metal Capacitors Failure Analysis

2005 ◽  
Author(s):  
Dat T. Nguyen ◽  
Frank Huang
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Visual Defect ◽  
Capacitor Plate ◽  
Chemical Etch ◽  
Defect Localization ◽  
Voltage Contrast

Abstract Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

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