Stacked Polysilicon/Metal Capacitors Failure Analysis

2005 ◽  
Author(s):  
Dat T. Nguyen ◽  
Frank Huang
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Visual Defect ◽  
Capacitor Plate ◽  
Chemical Etch ◽  
Defect Localization ◽  
Voltage Contrast

Abstract Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

Low Temperature Fault Isolation Using Soft Defect Localization

2012 ◽  
Author(s):  
Kristopher D. Staller
Keyword(s):  
Low Temperatures ◽  
Laser Scanning ◽  
Low Cost ◽  
Fault Isolation ◽  
Laser Scanning Microscopy ◽  
Cold Temperature ◽  
Multiple Point ◽  
Defect Localization ◽  
Low Levels

Abstract Cold temperature failures are often difficult to resolve, especially those at extreme low levels (< -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

Short Wavelength Probing for Fault Isolation Applications

2020 ◽  
Author(s):  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Vasanth Somasundaram ◽  
Phoa Angeline ◽  
Pey Kin Leong ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Spatial Resolution ◽  
Short Wavelength ◽  
Fault Isolation ◽  
Laser Probing ◽  
Successful Case ◽  
20 Nm

Abstract Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.

Case Study Failure Analysis of an Ultra-High Vacuum Enclosure Made of a Silicon Chip and Borosilicate Glass for the Cold Atom Laboratory

2017 ◽  
Author(s):  
Gil Garteiz ◽  
Javeck Verdugo ◽  
David Aveline ◽  
Eric Williams ◽  
Arvid Croonquist ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Borosilicate Glass ◽  
High Vacuum ◽  
Cold Atom ◽  
Fault Isolation ◽  
Ultra High Vacuum ◽  
Liquid Bath

Abstract In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.

Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

2001 ◽  
Author(s):  
C.C. Ooi ◽  
K.H. Siek ◽  
K.S. Sim
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Analysis Tool ◽  
Root Cause ◽  
Beam System ◽  
Defect Localization ◽  
Challenging Environment ◽  
Microprocessor Technology

Abstract Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Advanced CMOS Device Fault Isolation Using Frequency Mapping on Passive Structures

2013 ◽  
Author(s):  
S.H. Goh ◽  
B.L. Yeoh ◽  
G.F. You ◽  
W.H. Hung ◽  
Jeffrey Lam ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Device Failure ◽  
Functional Failure ◽  
Technology Node ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Scan Chains

Abstract Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.

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