Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.


Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.


2013 ◽  
Vol 2 (1) ◽  
pp. 57-67 ◽  
Author(s):  
Zaheer Khan ◽  
Qamer Faisal ◽  
Rabia Ahmad

Conventional UV-visible spectrophotometric and transmission electron microscopic technique were used to determine the morphology of silver nanoplates (AgNP) using Alstonia scholaris aqueous leaves extract for the first time. The visible spectra showed the presence of three well defined surface plasmon absorption (SRP) bands at 500, 550 and 675 nm which attributed to the anisotropic growth of Ag-nanoplates. Transmission electron microscopic (TEM) analysis of AgNP showed formation of truncated triangular, polyhedral with some irregular shapes nanoplates in the size range 7-20 nm. Cetyltrimethylammonium bromide (CTAB) has no significant effect on the shape of the spectra, position of SRP bands, size and the size distribution of AgNP. Effects of various [CTAB] were also discussed in the green extra-cellular synthesis of AgNP using Alstonia scholaris leaves extract.


Author(s):  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Vasanth Somasundaram ◽  
Phoa Angeline ◽  
Pey Kin Leong ◽  
...  

Abstract Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.


2017 ◽  
Vol 727 ◽  
pp. 280-283
Author(s):  
Xiao Ming Fu

Anatase TiO2 particles of about 20 nm in the diameter were successfully synthesized with Ti (SO4)2 as titanium source and stronger ammonia water as precipitant at 240°C for 48 h with pH=5 using the hydrothermal method. The samples were characterized by X-ray diffraction (XRD), transmission electron microscope (TEM) and ultraviolet-visible absorption spectroscopy (UV-VIS). XRD analysis showed that the phase of the samples was anatase TiO2. TEM analysis confirmed that TiO2 particles of about 50 nm in the diameter were obtained when the pH value was 0.12. With the increasement of the pH value, the size of as-prepared TiO2 particles became remarkably fine. However, with the further increase of the pH value, the size of TiO2 particles was not obvious. TiO2 particles of about 20 nm in the diameter were obtained when the pH value was 5. And UV-VIS results showed that the size of anatase TiO2 nanoparticles, which became small, was propitious to the blue shift of their absorption peak.


Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
J. Lam ◽  
T.H. Ng ◽  
G.R. Low ◽  
...  

Abstract With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.


Author(s):  
Liang Hong ◽  
Jia Li ◽  
Haifeng Wang

Abstract This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.


1997 ◽  
Vol 504 ◽  
Author(s):  
V. S. Touboltsev ◽  
E. Johnson ◽  
U. Dahmen ◽  
A. Johansen ◽  
L. Sarholt ◽  
...  

AbstracrSi<110> single crystals were implanted at a temperature of 835 K with 150 keV Pb+ ions to a fluence of 1·1020 m−2 corresponding to an average concentration of 2–3 at%. The implanted samples have been studied by Rutherford Backscattering (RBS)/channeling and transmission electron microscopy (TEM) techniques. In as-implanted samples the main fraction of implanted Pb was located on substitutional sites in the Si matrix thus providing a highly supersaturated solution of Pb in Si. Spontaneous precipitation of Pb, giving rise to formation of nanosized Pb inclusions, was found to take place only in the peak region of the implantation. TEM analysis showed that the Pb precipitates had sizes from about 2 to 20 nm and that they grew in parallel cube orientation relationship with the host matrix. The shape of the inclusions was found to be approximately cuboctahedral with poorly developed {111} and {100} facets.In-situ RBS/channeling heating/cooling experiments on both as-implanted samples and samples previously furnace-annealed at 1175 K showed a distinct melting/solidification hysteresis of the Pb inclusions around the bulk melting point for Pb at 600 K. These results were verified by in-situ TEM heating/cooling experiments on as-implanted samples.


Author(s):  
Jangwon Oh ◽  
Jonghyeop Kim ◽  
Taekwon Lee ◽  
Seungjoon Jeon ◽  
Won Kim ◽  
...  

Abstract The failure analysis using transmission electron microscopy (TEM) has been actively preceded in semiconductor industry. But due to the overlap issue and structural complexity of devices, it has become harder and harder to perform failure analysis using normal projected bright field (BF) and high angle annular dark field (HAADF) TEM images. To overcome these problems, 3-dimensional (3D) tomography technique has been suggested. In this work, we clarify the root cause of dark voltage contrast (DVC) failure at the bottom electrode contact region in PCRAM by using 3D tomography analysis. The 3D tomography samples were prepared in lamella shape by using focused ion beam (FIB). The electron energy loss spectroscopy (EELS) and 3D tomography analysis in scanning transmission electron microscope (STEM) HAADF mode were carried out. Through 3D tomography image reconstruction by AMIRA program, we observed ‘open contact fail’ between the BEC (Bottom Electrode Contact)-1 and the BEC (Bottom Electrode Contact)-2 at DVC region that could not be shown in 2D image.


Author(s):  
Haonan Bai ◽  
Lan Yin Lee ◽  
Yang Jing ◽  
Peter Floyd Salinas ◽  
Kok Keng Chua

Abstract Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.


Sign in / Sign up

Export Citation Format

Share Document