scholarly journals A High-Speed Bidirectional Register with Parallel Loading using single electron Threshold Logic Technology

2021 ◽  
pp. 394-408
Author(s):  
Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Tunnel Junctions ◽  
Linear Equations ◽  
Logic Gates ◽  
Single Electron ◽  
Nand Gate ◽  
Threshold Logic ◽  
Memory Element ◽  
Flip Flop ◽  
Complex Circuits

In this work we have concentrated our attention to a High Speed 4-bit Bidirectional Register with Parallel Loading counting on the principle of threshold logic gates (TLG). After determining the number of logic gates and other circuits needed to complete the desired circuit for our work, we implement some gates and circuits made up of tunnel junctions and capacitances. Some multi-inputs (greater than two) are designed or implemented with the assistance of modified version of the generic multi-input TLG. The types of gates suitable for the implementing the bidirectional Register are 3-input AND, 3-input NAND and 4-input OR gates, in addition an inverter and a more complex circuits like 4:1 Multiplexer are the part and parcel of the desired device. With the help of a 3-input AND gate and a 4-input OR gate, a 4:1 Multiplexer is built. By using the 3-input NAND gate a memory element – D Flip-flop is constructed. At last 4 number of 4:1 Multiplexers and another four number of D Flip-flops are combined in a parallel pattern to implement a 4-bit Bidirectional Register with Parallel Loading. Each component is made after analyzing their corresponding threshold linear equations. After constructing the threshold circuits, again they are formed by using the parameters as capacitors, tunnel junctions with their internal resistances. All the circuit, which are constructed, are verified by simulation with the help of SIMON and the result obtained are investigated and found that they are matched with the theoretical results. For comparing the fastness of our circuit with the CMOS-based or single electron transistor (SET) based circuit, the processing delays of all gates/ circuits are determined. How much power they consume are measured as well. Comparing the delays of CMOS-based and SET based circuit with the TLG based circuit we have decided that our 4-bit Bidirectional Register with Parallel Loading is speedier.

scholarly journals Enhanced All-Optical Y-Shaped Plasmonic OR, NOR And NAND Gate Models, Analyses, And Simulation For High Speed Computations

2021 ◽  
Author(s):  
Ipshitha Charles ◽  
Alluru Sreev ◽  
SabbiVamshi Krishna ◽  
Sandip Swarnakar ◽  
Santosh Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Extinction Ratio ◽  
Logic Gates ◽  
Nand Gate ◽  
Optical Logic ◽  
Metal Insulator Metal ◽  
All Optical ◽  
A New Technique ◽  
Complex Circuits

Abstract In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction of an all-optical OR, NOR, NAND gates based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB for NAND gate, 2 dB and 20.35 dB for NOR gate and 6 dB and 24.10 dB respectively. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

scholarly journals Enhanced All-optical Y-shaped Plasmonic NAND Gate Model, Analysis, and Simulation for High Speed Computations

2021 ◽  
Author(s):  
Ipshitha Charles ◽  
Alluru Sreev ◽  
SabbiVamshi Krishna ◽  
Sandip Swarnakar ◽  
Santosh Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Extinction Ratio ◽  
Logic Gates ◽  
Nand Gate ◽  
Optical Logic ◽  
Metal Insulator Metal ◽  
All Optical ◽  
A New Technique ◽  
Complex Circuits

Abstract In this digital era, all-optical logic gates (OLGs) proved its effectiveness in execution of high-speed computations. A unique construction for all optical NAND gate based on the notion of power combiner employing metal–insulator–metal (MIM) waveguide in the Y-shape in a minimal imprint of 6.2 µm × 3 µm is presented and the structure is evaluated by finite-difference time-domain (FDTD) technique. The insertion loss (IL) and extinction-ratio (ER) for proposed model are 6 dB and 27.76 dB. The simplified model is used in the construction of complex circuits to achieve greater efficiency, which contributes to the emergence of a new technique for designing plasmonic integrated circuits.

scholarly journals Design A High Speed Spin-Torque Transfer Magnetic Tunnel Junction (Stt-Mtj) NonVolatile Flip-Flops Based On Memory

2019 ◽  
Vol 8 (11) ◽  
pp. 3690-3694
Keyword(s):  
High Speed ◽  
Tunnel Junctions ◽  
Magnetic Tunnel Junctions ◽  
Magnetic Tunnel Junction ◽  
High Energy ◽  
Spin Transfer Torque ◽  
Spin Torque ◽  
Flip Flop ◽  
Spin Torque Transfer ◽  
Start Up

Basically, in low power applications, the energy should be harvested depend on the frequent interruptions. In this paper we proposed the design of spin-transfer torque magnetic tunnel junctions (STT-MTJs) non volatile based on flip flops based memory. The main intent of non volatile is to address the state of system by saving the memory. By using STT-MTJs based flip flop, high energy consumption will be obtained and there will be backup of the system. In CMOS the flip flop will used standard magnetic MRAM technology. The main intent of magnetic tunnel junctions is to store the data. The proposed non volatile flip flop will determine the delay and energy. Logic circuits are enabled using non volatility and this will reduce the start up latency. This start up latency ranges from micro seconds to hundred pico seconds. Here the information is stored using non volatile logic of memory. This process is done on pre chip basis. Hence compared to existed system, the proposed system gives effective results.

scholarly journals Microfluidic-based processors and circuits design

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Kasra Azizbeigi ◽  
Maysam Zamani Pedram ◽  
Amir Sanati-Nezhad
Keyword(s):  
Drug Testing ◽  
Experimental Testing ◽  
Logic Gates ◽  
Microfluidic Channels ◽  
Microfluidic Platforms ◽  
Flip Flop ◽  
Droplet Movement ◽  
Complex Circuits

AbstractDroplets produced within microfluidics have not only attracted the attention of researchers to develop complex biological, industrial and clinical testing systems but also played a role as a bit of data. The flow of droplets within a network of microfluidic channels by stimulation of their movements, trajectories, and interaction timing, can provide an opportunity for preparation of complex and logical microfluidic circuits. Such mechanical-based circuits open up avenues to mimic the logic of electrical circuits within microfluidics. Recently, simple microfluidic-based logical elements such as AND, OR, and NOT gates have been experimentally developed and tested to model basic logic conditions in laboratory settings. In this work, we develop new microfluidic networks, control the shape of channels and speed of droplet movement, and regulate the size of bubbles in order to extend the logical elements to six new logic gates, including AND/OR type 1, AND/OR type 2, NOT type 1, NOT type 2, Flip-Flop, Synchronizer, and a parametric model of T-junction as a bubble generator. We further designed and simulated a novel microfluidic Decoder 1 to 2, a Decoder 2 to 4, and a microfluidic circuit that combines several individual logic gates into one complex circuit. Further fabrication and experimental testing of these newly introduced logic gates within microfluidics enable implementing complex circuits in high-throughput microfluidic platforms for tissue engineering, drug testing and development, and chemical synthesis and process design.

scholarly journals Design and modelling of all-optical NAND gate using metal-insulator-metal (MIM) waveguides based Mach- Zehnder Interferometers for high-speed information processing

2021 ◽  
Author(s):  
Sandip Swarnakar ◽  
Siva Koti Reddy ◽  
Ramanand Harijan ◽  
Santosh Kumar
Keyword(s):  
Information Processing ◽  
Integrated Circuits ◽  
High Speed ◽  
Extinction Ratio ◽  
Logic Gates ◽  
Nand Gate ◽  
Metal Insulator ◽  
Metal Insulator Metal ◽  
All Optical ◽  
Mathematical Computation

Abstract All the basic logic gates play a major role in carrying out the mathematical computation. The drawbacks of conventional electronics are alleviated by all-optical integrated circuits with a great application of high-speed computing and information processing. In this paper, plasmonic metal-insulator-metal (MIM) waveguides have an excellent property of propagating the surface plasmons beyond the diffraction limit up to deep sub-wavelength scale. All-optical NAND gate design is optimized by using MIM plasmonic waveguide-based Mach-Zehnder Interferometers (MZIs) in the footprint of 36 µm × 8 µm that works at 1.55 µm operating wavelength. The better performance of the proposed device is achieved, such as the extinction ratio is 10.55 dB, insertion loss is obtained as 0.506 dB, and response time is 262 ps. The proposed design is verified by using the finite-difference time-domain (FDTD) technique and further analysis are carried out by mathematical computation and MATLAB simulation results.

An On-Chip Digital Monostable Multivibrator Using Inverter-based Delay Chains

2019 ◽  
Vol 28 (04) ◽  
pp. 1920001
Author(s):  
Meilin Wan ◽  
Yin Zhang ◽  
Ming Zhang ◽  
Haoshuang Gu
Keyword(s):  
Signal Processing ◽  
Logic Gates ◽  
Output Pulse ◽  
Effective Area ◽  
Nand Gate ◽  
Cmos Process ◽  
Monostable Multivibrator ◽  
Flip Flop ◽  
Basic Circuit ◽  
On Chip

Monostable multivibrator or one-shot timer is widely used in signal processing. In this paper, a simple and useful way to realize retriggerable monostable multivibrator by using digital logic gates is presented. The basic circuit is composed of one D flip-flop, one NAND gate, one inverter (INV) and two inverter-based delay chains. The width of the output pulse is adjusted through tuning the delay of the inverter-based delay chain. The retriggerable characteristic is realized by resetting all the delayed signals when new triggering occurs in the current monostable period. The basic circuit is designed and fabricated on-chip using a 180[Formula: see text]nm standard CMOS process with effective area less than 1200[Formula: see text][Formula: see text]m2. The retriggerable version is realized in a FPGA platform. Both simulated and measured results are in agreement with the theoretical analysis.

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