scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

scholarly journals A High-Speed Bidirectional Register with Parallel Loading using single electron Threshold Logic Technology

2021 ◽  
pp. 394-408
Author(s):  
Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Tunnel Junctions ◽  
Linear Equations ◽  
Logic Gates ◽  
Single Electron ◽  
Nand Gate ◽  
Threshold Logic ◽  
Memory Element ◽  
Flip Flop ◽  
Complex Circuits

In this work we have concentrated our attention to a High Speed 4-bit Bidirectional Register with Parallel Loading counting on the principle of threshold logic gates (TLG). After determining the number of logic gates and other circuits needed to complete the desired circuit for our work, we implement some gates and circuits made up of tunnel junctions and capacitances. Some multi-inputs (greater than two) are designed or implemented with the assistance of modified version of the generic multi-input TLG. The types of gates suitable for the implementing the bidirectional Register are 3-input AND, 3-input NAND and 4-input OR gates, in addition an inverter and a more complex circuits like 4:1 Multiplexer are the part and parcel of the desired device. With the help of a 3-input AND gate and a 4-input OR gate, a 4:1 Multiplexer is built. By using the 3-input NAND gate a memory element – D Flip-flop is constructed. At last 4 number of 4:1 Multiplexers and another four number of D Flip-flops are combined in a parallel pattern to implement a 4-bit Bidirectional Register with Parallel Loading. Each component is made after analyzing their corresponding threshold linear equations. After constructing the threshold circuits, again they are formed by using the parameters as capacitors, tunnel junctions with their internal resistances. All the circuit, which are constructed, are verified by simulation with the help of SIMON and the result obtained are investigated and found that they are matched with the theoretical results. For comparing the fastness of our circuit with the CMOS-based or single electron transistor (SET) based circuit, the processing delays of all gates/ circuits are determined. How much power they consume are measured as well. Comparing the delays of CMOS-based and SET based circuit with the TLG based circuit we have decided that our 4-bit Bidirectional Register with Parallel Loading is speedier.

scholarly journals Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

2021 ◽  
pp. 07-24
Author(s):  
Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Logic Gate ◽  
Clear Understanding ◽  
Threshold Logic ◽  
Xor Gate ◽  
Multiple Input ◽  
Exclusive Or ◽  
Hypercube Network ◽  
Or Gate

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.

Low-cost BSA technique for threshold-logic gate based multiplier implementations

1997 ◽  
Vol 33 (12) ◽  
pp. 1028
Author(s):  
J.M. Quintana ◽  
M.J. Avedillo ◽  
A. Rueda
Keyword(s):  
Low Cost ◽  
Logic Gate ◽  
Threshold Logic

scholarly journals High Speed All-Optical Logic Gate Using QD-SOA and its Application

2017 ◽  
Author(s):  
Shuai Zhao ◽  
Hongyu Hu
Keyword(s):  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Boolean Logic ◽  
Hole Burning ◽  
Spectral Hole Burning ◽  
Optical Logic ◽  
Carrier Heating ◽  
Optical Logic Gates ◽  
All Optical

The scheme to realize high speed (~250Gb/s) all-optical Boolean logic gates using semiconductor optica amplifiers with quantum-dot (QD-SOA) is introduced and analyzed in this review. Numerical simulation method was presented by solving the rate equation and taking into account nonlinear dynamics including carrier heating and spectral hole-burning. Binary phase shift keyed (BPSK) signal and on-off keyed signal are used to generate high speed all-optical logic gates. The applications based on all-optical logic gates such as, all-optical latches, pseudo random bit sequence (PRBS) generation and all-optical encryption, are also discussed in this review. Results show that the scheme based on QD-SOA is a promising method for the realization of high speed all-optical communication system in the future.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
S. Rasoul Faraji ◽  
Pierre Abillama ◽  
Kia Bazargan
Keyword(s):  
Discrete Cosine Transform ◽  
Video Processing ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Logic Gates ◽  
Cosine Transform ◽  
Real Time Processing ◽  
Coefficient Multiplier ◽  
Encoding Method

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

Optimization of an All-Optical Photonic Crystal NOT Logic Gate Using Switch Based on Nonlinear Kerr Effect and Ring Resonator

2020 ◽  
Vol 18 (2) ◽  
pp. 89-94 ◽  
Author(s):  
Elhachemi Kouddad ◽  
Rafah Naoum
Keyword(s):  
Photonic Crystal ◽  
Kerr Effect ◽  
High Speed ◽  
Logic Gate ◽  
Contrast Ratio ◽  
Logic Gates ◽  
Square Lattice ◽  
All Optical ◽  
Easy Integration ◽  
Nano Crystal

In this paper, the use of the Kerr effect in a two-dimensional square lattice of In0.82Ga0.18As0.40P0.60 rods in photonic crystal proposes an ultra-compact all-optical NOT logic gate. The main device operation is based on the concept of all the optical switches. In our work, the novelty lies in the design of a new simple nonlinear ring based on the combination of silicon nano-crystal "Si–Nc/In0.82Ga0.18As0.40P0.60" materials that can be used. The contrast ratio and delay time for the proposed NOT logic gate are respectively 25.52 dB and 0.66 ps. The structure size is equal to 168 μm2. Designed logic gates are characterized by low energy consumption, high-speed response, compactness and easy integration. All simulations are based on Non-Linear-Finite Difference Time Domain (NL-FDTD) and Plane Wave Expansion (PWE) numerical methods.

Low power, high speed, charge recycling CMOS threshold logic gate

2001 ◽  
Vol 37 (17) ◽  
pp. 1067 ◽  
Author(s):  
P. Celinski ◽  
J.F. López ◽  
S. Al-Sarawi ◽  
D. Abbott
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gate ◽  
Threshold Logic ◽  
Charge Recycling

scholarly journals Magnitude Comparator Realization using Threshold Logic

2019 ◽  
Vol 8 (3) ◽  
pp. 1917-1921
Keyword(s):  
Logic Gate ◽  
Vlsi Design ◽  
Logic Gates ◽  
Design System ◽  
Logic Design ◽  
Weighted Sum ◽  
Threshold Logic ◽  
Activation Threshold ◽  
Traditional Logic ◽  
Simulation Tools

Threshold logic design can be regarded as an alternative method of traditional logic gate design. Threshold logic can be considered as the primary logic of brain. Neurons can be considered as threshold logic gates. Each neuron fires when its activation threshold is crossed. The basic idea behind threshold logic is threshold decision principle. Threshold decision principle checks whether the weighted sum of inputs crosses a threshold and accordingly output is defined. Several implementations for threshold logic were proposed. Resistive threshold logic is a new method for threshold logic implementation. In this paper, using the concept of resistive threshold logic, a magnitude comparator is realized. LTSpiceIV and Electric VLSI Design System are the simulation tools used in this work.

Low Power High Speed MISTY1 Cryptography Approaches

2018 ◽  
Vol 27 (13) ◽  
pp. 1850200 ◽  
Author(s):  
Abdoul Rjoub ◽  
Ehab M. Ghabashneh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Logic Gate ◽  
Logic Gates ◽  
Portable Devices ◽  
Silicon Area ◽  
Dynamic Power ◽  
Conventional Design ◽  
Reduction Approach

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and efficient encryption/decryption algorithms. Recently, efficient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetime of battery by reducing the total silicon capacitance and minimizing the switching activity. This paper presents two approaches to reduce the number of logic gates at S7 and S9 of MISTY1 in order to reduce the total delay time, power dissipation and silicon area. The Logic Gate Reduction Approach (LGRA) reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the Duplicated Gate Reduction Approach (DGRA) removes the redundant XOR and AND logic gates which form the S7 and S9 blocks ciphers. The LGRA approach shows that the throughput enhanced by 21.1% compared to the conventional design, the silicon area reduced by 26.8%, while the dynamic power dissipation is reduced by 21.7% on average. The DGRA approach shows that the throughput enhanced by 3.8% compared to the conventional design, the silicon area reduced by 31.7%, while the dynamic power dissipation is reduced by 27% on average. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

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