scholarly journals Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 749
Author(s):  
Fábio Batagin Armelin ◽  
Lírida Alves de Barros Naviner ◽  
Roberto d’Amore
Keyword(s):  
Radiation Effects ◽  
Estimation Error ◽  
Soft Errors ◽  
Soft Error ◽  
The Other ◽  
Single Event ◽  
Single Event Transient ◽  
Logic Simulation ◽  
Advantages And Disadvantages ◽  
Simulation Based

Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.

Single-Event Transient Case Study for System-Level Radiation Effects Analysis

2021 ◽  
pp. 1-1
Author(s):  
Michael J. Campola ◽  
Rebekah A. Austin ◽  
Edward P. Wilcox ◽  
Hak S. Kim ◽  
Raymond L. Ladbury ◽  
...  
Keyword(s):  
Radiation Effects ◽  
System Level ◽  
Single Event ◽  
Single Event Transient ◽  
Transient Case

scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 117-120 ◽  
Author(s):  
Robert Baumann
Keyword(s):  
Soft Errors ◽  
Deep Submicron ◽  
Soft Error ◽  
Mitigation Strategies ◽  
Single Event ◽  
Radiation Mechanisms ◽  
Silicon Technology ◽  
Single Event Upsets ◽  
Radiation Induced ◽  
Considerable Concern

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

scholarly journals Integrated Silicon Photonics for Enabling Next-Generation Space Systems

Photonics ◽  
2021 ◽  
Vol 8 (4) ◽  
pp. 131
Author(s):  
George N. Tzintzarov ◽  
Sunil G. Rao ◽  
John D. Cressler
Keyword(s):  
Silicon Photonics ◽  
Radiation Effects ◽  
Space Systems ◽  
Single Event ◽  
Transient Effects ◽  
Single Event Transient ◽  
Space Applications ◽  
Silicon Waveguides ◽  
Current State ◽  
Integrated Silicon Photonics

A review of silicon photonics for space applications is presented. The benefits and advantages of size, weight, power, and cost (SWaP-C) metrics inherent to silicon photonics are summarized. Motivation for their use in optical communications systems and microwave photonics is addressed. The current state of our understanding of radiation effects in silicon photonics is included in this discussion. Total-ionizing dose, displacement damage, and single-event transient effects are discussed in detail for germanium-integrated photodiodes, silicon waveguides, and Mach-Zehnder modulators. Areas needing further study are suggested.

scholarly journals RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 690 ◽  
Author(s):  
V. Díez-Acereda ◽  
Sunil L. Khemchandani ◽  
J. del Pino ◽  
S. Mateos-Angulo
Keyword(s):  
Radiation Effects ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
High Energy ◽  
Frequency Synthesizers ◽  
High Energy Particle ◽  
Single Event ◽  
Single Event Transient ◽  
Effects Of Radiation ◽  
Radiation Hardening By Design

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

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