scholarly journals InP-Based Foundry PICs for Optical Interconnects

2019 ◽  
Vol 9 (8) ◽  
pp. 1588 ◽  
Author(s):  
Francisco M. Soares ◽  
Moritz Baier ◽  
Tom Gaertner ◽  
Norbert Grote ◽  
Martin Moehrle ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Low Cost ◽  
Fabrication Process ◽  
Input Output ◽  
Fully Integrated ◽  
Technology Platforms ◽  
Optical Applications ◽  
High Level ◽  
Surface Coupling

This paper describes a fabrication process for realizing Indium-Phosphide-based photonic-integrated circuits (PICs) with a high level of integration to target a wide variety of optical applications. To show the diversity in PICs achievable with our open-access foundry process, we illustrate two examples: a fully-integrated 20 Gb/s dual-polarization electro-absorption-modulated laser, and a balanced detector composed of avalanche photodiodes for detection of 28 Gb/s optical signals. On another note, datacenters are increasingly relying on hybrid integration of PICs from different technology platforms to increase transmission capacity, while simultaneously lowering cost, size, and power consumption. Several technology platforms require surface coupling rather than the traditional edge coupling to couple the light from one PIC to another. To accommodate the surface-coupling approach in our integration platform, we have developed a strategy to transfer the following optical Input/Output devices into our fabrication process: grating couplers, and vertical mirrors. In addition, we introduced etched facets into the process to improve the usability of our edge-coupling elements. We believe that the additional flexibility in Input/Output interfacing combined with the integration of multiple devices onto one PIC to reduce the number of PIC-to-PIC alignments can contribute significantly to the development of compact, low-cost, and high-performance datacenter modules.

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

scholarly journals Low cost and green preparation process for α-Fe2O3@gum arabic electrode for high performance sodium ion batteries

2017 ◽  
Vol 5 (5) ◽  
pp. 2102-2109 ◽  
Author(s):  
Li Xu ◽  
Hansinee Sitinamaluwa ◽  
Henan Li ◽  
Jingxia Qiu ◽  
Yazhou Wang ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Gum Arabic ◽  
Fabrication Process ◽  
Sodium Ion ◽  
Sodium Ion Batteries ◽  
Preparation Process ◽  
Water Based ◽  
Electrode Fabrication ◽  
First Time

A high performance α-Fe2O3 electrode is prepared via a green gum arabic-water based electrode fabrication process for SIBs for the first time.

Device Limitations

1987 ◽  
Vol 108 ◽  
Author(s):  
Robert W. Keyes
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Large System ◽  
Semiconductor Technology ◽  
Input Output ◽  
Packaging Technology ◽  
Large Systems ◽  
Levels Of Integration

ABSTRACTPackaging technology must deal with the inexorable trend of semiconductor technology towards higher levels of integration. Extrapolation of present trends suggests that chips with 100 million devices will be produced by the end of the present century. The ability of technology to miniaturize pin-outs will limit the utilization of all of these devices for purposes other than memory. This limitation plus problems of supplying power and removing heat means that chips for high-performance large systems, where the demand for pins follows a well known rule, will probably be limited to levels of integration less than 100,000. A model of large system wiring shows that large increases in the density of wires in system packages and in the rate at which heat can be removed will be needed.Less severe limitations apply to low cost applications. No large increase in power per chip can be anticipated. However, more powerful microprocessors will become available and will need increased amounts of input-output capability.

Passivating Organic Coatings with Silicone Gels: The Correlation Between the Material Cure & its Electrical Reliability

1989 ◽  
Vol 154 ◽  
Author(s):  
C. P. Wong
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Protective Coatings ◽  
Low Cost ◽  
Chip Surface ◽  
Surface Protection ◽  
Cure Time ◽  
Silicone Gels ◽  
Cure Temperature ◽  
Electrical Reliability

AbstractSilicone gels are becoming some of the most accepted protective coatings for VLSI integrated circuits due to their excellent electrical, thermal, and soft gel-like nature and properties, as well as their ultra-purity and ability to protect IC devices against severe environments. Recent studies indicate that proper IC Chip surface protection with high performance silicone gels in low-cost, non-hermetic plastic packaging might well replace the conventional hermetic ceramic packaging. This paper describes the use of the soft silicone gels and coatings in IC devices. It also describes the correlation between the material cure temperature and cure time versus their adhesion and electrical reliability during 85°C, 85% RH and bias accelerating testing.

Thin-film Micro-Batteries Based on Metal Nanoparticles

2012 ◽  
Vol 1440 ◽  
Author(s):  
Shuang Peng ◽  
Wenjun Du ◽  
Leela Rakesh ◽  
Axel Mellinger ◽  
Tolga Kaya
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Metal Nanoparticles ◽  
High Performance ◽  
Low Voltage ◽  
Low Cost ◽  
Open Circuit ◽  
Energy Storage And Conversion ◽  
Battery Capacity ◽  
Zn Nanoparticles

ABSTRACTWe proposed the use of Copper (Cu) and Zinc (Zn) nanoparticles as the electrodes for thin-film microbatteries in the applications of micro-scale sensors. Compared to the widely used lithium-based batteries, Cu and Zn nanoparticles are less expensive, less prone to oxidation (thus involving simpler fabrication steps) and flammability, safe to use, and only requires very simple fabrication processes.Even though the voltage output is inherently smaller (∼1V) than conventional lithium-based batteries, it is sufficient for low-voltage Integrated Circuits (IC) technologies such as 130 nm and 90 nm channel length transistor processes.Commercial paper will be used as the separator to demonstrate the battery capacity. Paper that acts as the separator is slurry-casted with nanoparticles (30-40 nm in size) on both sides. The thickness of the metal nanoparticles-coated thin films and the paper separator are 1 μm and 100 μm, respectively.The electrodes were developed to achieve high conductivity (lower than 1 (Ω·cm)-1) with smooth surface, good adhesion, and flexibility. The metal nanoparticles will be formulated to slurry solutions for screen printing or ink-jet printing for the battery fabrication. For fabrication purposes, the slurries viscosity is approximately in the range of 10-12 cPs at the operating temperature, a surface tension between 28-33 dynes/cm. During the fabrication process including printing/coating and sintering, reductive environment is required to minimize the oxidation. AFM (Atomic Force Microscopy) and EDS (Energy Dispersive Spectroscopy) results will be employed to demonstrate the surface morphology as well as the percentages of metal oxides. Batteries will be tested with and without an ionic liquid for comparison. Humidity effects on the battery performance will also be discussed.Different geometries that are designed to make the batteries with higher voltage or charge will be proposed. Characterization results will include the open-circuit voltage, dielectric property, charging and discharging curve, capacitance and capacity, AFM of the surface test, EDS of the electrodes and the SEM (Scanning Electron microscopy) of the particles.Ourresearch suggest that conductive paper can be scalable and could make high-performance energy storage and conversion devices at low cost and would bring new opportunities for advanced applications.

Micromachined W-Band Waveguide Duplexer Design Based on MEMS Technology

2013 ◽  
Vol 562-565 ◽  
pp. 1098-1102
Author(s):  
Hui Liang Liu ◽  
Chen Xu Zhao ◽  
Ling Li ◽  
Ze Wen Liu
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Return Loss ◽  
Low Cost ◽  
Digital Signal ◽  
Fabrication Process ◽  
Production Program ◽  
W Band ◽  
Mems Technology ◽  
Rf Performance

This paper presents a novel high performance W-band MEMS duplexer for digital signal transceiver applications. The design of duplexer filters follows the insertion loss method with a Chebyshev polynomial to meet the desired spectral responses. The insertion loss and return loss of the optimized duplexer are -0.3dB and -18dB respectively, while the isolation between two pass bands is -55dB. A micro-fabrication process is designed based on MEMS technology. The deep reactive ion etching (DRIE) is used for high-aspect-ratio filter cavity mold structure. Micro-electroforming, plastic embossing, and electroplating techniques are used for low-cost and high-precision mass production program for the duplexer. Fabrication error tolerance is analyzed and it is reasonable to control the shift of frequency and return loss in the range of 0.05GHz and 2dB respectively with the designed fabrication process based on MEMS technology. It proves that the proposed micromachining fabrication technique is suitable for high performance W-band waveguide filter and duplexer design in terms of stability of RF performance.

scholarly journals THE SUPERCOMPUTER TOOLKIT AND ITS APPLICATIONS

1998 ◽  
Vol 09 (03) ◽  
pp. 807-846 ◽  
Author(s):  
JACOB KATZENELSON ◽  
ALEXANDER GOIKHMAN
Keyword(s):  
Small Groups ◽  
High Performance ◽  
Low Cost ◽  
Weather Prediction ◽  
Paper Briefly ◽  
Communication Devices ◽  
Software Modules ◽  
High Level ◽  
Interconnect Technology ◽  
Scientific Engineering

The Supercomputer Toolkit is a family of hardware and software modules from which high-performance special-purpose computers for scientific/engineering use can be easily constructed and programmed. The hardware modules include processors, memory, I/O devices and communication devices. The software modules include an operating system, compilers, debuggers, simulators, scientific libraries, and high-level front ends. When faced with a suitable problem, the engineer/scientist connects the modules by means of static-interconnect technology and constructs a problem-specific parallel computation network. The network is loaded from a workstation that serves as a host. When the program is run, results are collected and displayed by the host. The host handles files, does compilation, etc. The computation network, the Toolkit, does the heavy computation. In addition to high performance, the advantage of the Toolkit is its low cost which makes it potentially affordable by small groups as their main number crunching computer. This paper is concerned with the Toolkit version built at the Technion, which is a second generation of the MIT version.1 The paper briefly describes the hardware and software of this new version and its application to elastic-plastic flow, weather prediction and the simulation of electronic circuits. The main topic of the application section is the relation between the Toolkit configuration and the computation structure of these applications. The paper discusses conclusions related to the hardware and software as well as to the techniques for applying the system.

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