scholarly journals A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

Coatings ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 514 ◽  
Author(s):  
Feng-Tso Chien ◽  
Kuang-Po Hsueh ◽  
Zhen-Jie Hong ◽  
Kuan-Ting Lin ◽  
Yao-Tsung Tsai ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Impact Ionization ◽  
Thin Film Transistor ◽  
Ionization Rate ◽  
Field Plate ◽  
Current Path ◽  
Plate Design ◽  
Impact Ionization Rate ◽  
A Current

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.

scholarly journals Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

Membranes ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 103
Author(s):  
Feng-Tso Chien ◽  
Jing Ye ◽  
Wei-Cheng Yen ◽  
Chii-Wen Chen ◽  
Cheng-Li Lin ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Electric Fields ◽  
Systems Engineering ◽  
Impact Ionization ◽  
Thin Film Transistor ◽  
Ionization Rate ◽  
Drain Side ◽  
Output Characteristics ◽  
Lightly Doped Drain

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

scholarly journals Double-Gate Two-Step Source/Drain Poly-Si Thin-Film Transistor

Coatings ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 233 ◽  
Author(s):  
Feng-Tso Chien ◽  
Chih-Ping Hung ◽  
Hsien-Chin Chiu ◽  
Tsung-Kuei Kang ◽  
Ching-Hwa Cheng ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Stress Test ◽  
Thin Film Transistor ◽  
Double Gate ◽  
Silicon Thin Film ◽  
Hot Carrier ◽  
Single Top ◽  
Lightly Doped Drain ◽  
A Current

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device.

Polysilicon High-Voltage TFT with Field-Plate-Controlled Offset Region

1990 ◽  
Vol 182 ◽  
Author(s):  
T. Y. Huang ◽  
I. W. Wu ◽  
A. G. Lewis ◽  
A. Chiang ◽  
R. H. Bruce
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Ion Implantation ◽  
High Voltage ◽  
Thin Film Transistor ◽  
Large Area ◽  
Process Flow ◽  
Field Plate ◽  
Turn On ◽  
Lightly Doped Drain

AbstractAn improved polysilicon high voltage thin film transistor (HVTFT) structure with field-plate-controlled offset region (FP-HVTFT) is proposed for eliminating the current-pinching phenomena often observed in the conventional offset-gate polysilicon HVTFTs. The new metal field plate serves, in lieu of ion implantation, to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends of the offset region, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current-pinching effects are consistently obtained. Moreover, the new FP-HVTFT also eliminates the lightly-doped-drain implant normally required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process flow.

Simulated Programming Characteristics of Stacked-Gate Flash Memories with High-k Tunnel Dielectrics

2011 ◽  
Vol 383-390 ◽  
pp. 5851-5854
Author(s):  
Yung Yu Chen
Keyword(s):  
Electric Field ◽  
Impact Ionization ◽  
Ionization Rate ◽  
Hot Electron ◽  
Coupling Ratio ◽  
Flash Memories ◽  
High Permittivity ◽  
Hot Electron Injection ◽  
High K ◽  
Impact Ionization Rate

Due to the reduced gate coupling ratio, the channel Fowler-Nordheim (CFN) programming speed of stacked-gate flash memories with high-permittivity (k) tunnel dielectrics (TDs) is helpless in operation voltage reduction. Although the electric field on high-k tunnel dielectrics is lower than SiO2 tunnel oxide, enhanced impact ionization rate and lower barrier height contribute to higher channel hot-electron (CHE) injection current and efficiency. Consequently, high-k TDs are only effective for the memories programmed with hot electron injection rather than FN tunneling, which is suitable for the NOR-type stacked-gate flash memories.

scholarly journals High impact ionization rate in silicon by sub-picosecond THz electric field pulses (Conference Presentation)

2017 ◽  
Author(s):  
Abebe T. Tarekegne ◽  
Krzysztof Iwaszczuk ◽  
Hideki Hirori ◽  
Koichiro Tanaka ◽  
Peter U. Jepsen
Keyword(s):  
Electric Field ◽  
Impact Ionization ◽  
Ionization Rate ◽  
High Impact ◽  
Impact Ionization Rate

Theoretical Prediction of Zinc Blende Phase GaN Avalanche Photodiode Performance Based on Numerically Calculated Electron and Hole Impact Ionization Rate Ratio

1996 ◽  
Vol 423 ◽  
Author(s):  
J. Kolnik ◽  
I. H. Oguzman ◽  
K. F. Brennan ◽  
R. Wang ◽  
P. P. Ruden
Keyword(s):  
Electric Field ◽  
Applied Electric Field ◽  
Impact Ionization ◽  
Full Range ◽  
Avalanche Photodiode ◽  
Ionization Rate ◽  
Zinc Blende ◽  
Valence Bands ◽  
Impact Ionization Rate ◽  
Ionization Rates

AbstractIn this paper, we present the first calculations of the electron and hole initiated interband impact ionization rate in zinc blende phase GaN as a function of the applied electric field strength. The calculations are performed using an ensemble Monte Carlo simulator including the full details of the conduction and valence bands along with a numerically determined, wave-vector dependent interband ionization transition rate determined from an empirical pseudopotential calculation. The first four conduction bands and first three valence bands, which fully comprise the energy range of interest for device simulation, are included in the analysis. It is found that the electron and hole ionization rates are comparable over the full range of applied electric field strengths examined. Based on these calculations an avalanche photodiode, APD, made from bulk zinc blende GaN then would exhibit poor noise and bandwidth performance. It should be noted however, that the accuracy of the band structure employed and the scattering rates is presently unknown since little experimental information is available for comparison. Therefore, due to these uncertainties, it is difficult to unequivocally conclude that the ionization rates are comparable.

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