scholarly journals A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 530
Author(s):  
Stefan Pechmann ◽  
Timo Mai ◽  
Matthias Völkel ◽  
Mamathamba K. Mahadevaiah ◽  
Eduardo Perez ◽  
...  
Keyword(s):  
Voltage Drop ◽  
Random Access ◽  
Process Variations ◽  
Resistive Random Access Memory ◽  
Cmos Process ◽  
Programming System ◽  
Analog Memory ◽  
Wide Range ◽  
Multi Level ◽  
New Memory Technology

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

scholarly journals Multi-Level Switching of Al-Doped HfO2 RRAM with a Single Voltage Amplitude Set Pulse

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 731
Author(s):  
Jinfu Lin ◽  
Shulong Wang ◽  
Hongxia Liu
Keyword(s):  
Random Access ◽  
Resistive Random Access Memory ◽  
Programming Algorithm ◽  
Voltage Amplitude ◽  
Strength Change ◽  
Value Range ◽  
Multi Level ◽  
Conductance States ◽  
Switching Characteristics ◽  
Sandwiched Structure

In this paper, the resistive switching characteristics in a Ti/HfO2: Al/Pt sandwiched structure are investigated for gradual conductance tuning inherent functions. The variation in conductance of the device under different amplitudes and voltage pulse widths is studied. At the same time, it was found that the variation in switching parameters in resistive random-access memory (RRAM) under impulse response is impacted by the initial conductance states. The device was brought to a preset resistance value range by energizing a single voltage amplitude pulse with a different number of periodicities. This is an efficient and simple programming algorithm to simulate the strength change observed in biological synapses. It exhibited an on/off of about 100, an endurance of over 500 cycles, and a lifetime (at 85 °C) of around 105 s. This multi-level switching two-terminal device can be used for neuromorphic applications to simulate the gradual potentiation (increasing conductance) and inhibition (decreasing conductance) in an artificial synapse.

scholarly journals Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 21
Author(s):  
Mohamed R. Elmezayen ◽  
Wei Hu ◽  
Amr M. Maghraby ◽  
Islam T. Abougindia ◽  
Suat U. Ay
Keyword(s):  
Process Variations ◽  
Schmitt Trigger ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Original Design ◽  
Accurate Analysis ◽  
Single Input Single Output ◽  
Analysis And Design ◽  
Wide Range ◽  
Single Input

Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

Analog memory characteristics of 1T1R MoOx resistive random access memory

2016 ◽  
Author(s):  
Mingyu Jo ◽  
Reon Katsumura ◽  
Atsushi Tsurumaki-Fukuchi ◽  
Masashi Arita ◽  
Yasuo Takahashi ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Analog Memory ◽  
Memory Characteristics

VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT

SPIN ◽  
2012 ◽  
Vol 02 (03) ◽  
pp. 1240008
Author(s):  
HAI (HELEN) LI ◽  
ZHENYU SUN
Keyword(s):  
Cell Structure ◽  
Random Access ◽  
Process Variations ◽  
Spin Transfer Torque ◽  
Yield Enhancement ◽  
Cmos Process ◽  
Standby Power ◽  
Magnetic Tunneling ◽  
Non Destructive ◽  
Self Reference

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips. In this paper, we propose a novel voltage-driven non-destructive self-reference sensing scheme (NDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16 Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous NDRS scheme while improving the sense margin by 5 × with the similar access performance and power.

Sign in / Sign up

Export Citation Format

Share Document