scholarly journals Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 8 ◽  
Author(s):  
Young Kim ◽  
Jin Lee ◽  
Geon Kim ◽  
Taesik Park ◽  
Hui Kim ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Channel Length ◽  
Subthreshold Slope ◽  
Access Memory ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Saddle Type ◽  
Partial Isolation

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and Ioff characteristics as gate channel length decreased.

scholarly journals Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

2018 ◽  
Author(s):  
Myoung Jin Lee ◽  
young kwon kim ◽  
taesik park ◽  
geon kim ◽  
jin sung lee ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Channel Length ◽  
Subthreshold Slope ◽  
Access Memory ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Saddle Type ◽  
Partial Isolation

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.

scholarly journals Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1051 ◽  
Author(s):  
Songyi Yoo ◽  
Woo-Kyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
The Body ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Transient Performance ◽  
Drain Voltage ◽  
Access Memory ◽  
Short Channel

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.

Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

1997 ◽  
Vol 490 ◽  
Author(s):  
Julie Y. H. Lee ◽  
Tom C. H. Lee ◽  
Mike Embry ◽  
Keenan Evans ◽  
Dan Koch ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Drift Diffusion ◽  
Short Channel ◽  
Short Channel Effect ◽  
Dopant Segregation ◽  
Channel Effect ◽  
Substrate Doping ◽  
Compositional Segregation

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

Electrical characteristics and short-channel effect ofc-axis aligned crystal indium gallium zinc oxide transistor with short channel length

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EF03 ◽  
Author(s):  
Yoshiyuki Kobayashi ◽  
Shinpei Matsuda ◽  
Daisuke Matsubayashi ◽  
Hideomi Suzawa ◽  
Masayuki Sakakura ◽  
...  
Keyword(s):  
Zinc Oxide ◽  
Channel Length ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Indium Gallium

scholarly journals PERFORMANCE COMPARISON OF BULK FINFET WITH SOI FINFET IN NANO-SCALE REGIME

2013 ◽  
pp. 104-107
Author(s):  
SUMANLATA TRIPATHI ◽  
RAMANUJ MISHRA ◽  
SANDEEP MISHRA ◽  
VIRENDRA PRATAP YADAV ◽  
R.A. MISHRA
Keyword(s):  
Performance Improvement ◽  
Performance Comparison ◽  
Doping Profile ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Short Channel Effect ◽  
Soi Mosfet ◽  
Channel Effect ◽  
Simulation Results ◽  
The Ideal

This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also compares the performance improvement of Multi-gate Bulk and SOI MOSFET over Single-gate bulk and SOI MOSFET.The simulation results are obtained with the help of TCAD 3-D device simulator are well matched with the ideal characteristics.

scholarly journals Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1908
Author(s):  
Jin-sung Lee ◽  
Jin-hyo Park ◽  
Geon Kim ◽  
Hyun Duck Choi ◽  
Myoung Jin Lee
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Transistor Structure ◽  
Current Leakage ◽  
Buried Channel ◽  
Partial Isolation ◽  
20 Nm

In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current.

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