Effects of Compositional Segregation and Short Channel on Threshold Voltage of nMOSFET

ABSTRACTThis study calculates the threshold voltage (VT) roll-off behavior caused by short channel effect (SCE) as a result of scaling and the reverse short-channel effect (RSCE) due to B segregation around source and drain junctions by using the 2D device simulator - SILVACO™-ATLAS. The simulation results are comparable with the experimental data. It suggests that the drift diffusion physics can predict SCE and RSCE very well to sub-0.25μ Si n-MOSFET devices. The modeling results indicate the VT roll off at shorter channel length for devices with higher substrate doping concentration. VT increases if the local p-dopant segregation exists around the source and drain junction. It is observed that RSCE is more significant for devices with lower substrate doping concentration and shorter channel length.

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Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0106 ◽

2012 ◽

Author(s):

Yuk L. Tsang ◽

Xiang D. Wang ◽

Reyhan Ricklefs ◽

Jason Goertz

Keyword(s):

Threshold Voltage ◽

Electrical Characterization ◽

Cmos Technology ◽

Short Channel ◽

Visual Defect ◽

Subthreshold Region ◽

Short Channel Effect ◽

Channel Effect ◽

Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

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Interface Interstitial Recombination Rate and the Reverse Short Channel Effect

MRS Proceedings ◽

10.1557/proc-568-213 ◽

1999 ◽

Vol 568 ◽

Cited By ~ 1

Author(s):

M.E. Rubin ◽

S. Saha ◽

J. Lutze ◽

F. Nouri ◽

G. Scott ◽

...

Keyword(s):

Threshold Voltage ◽

Recombination Rate ◽

Gate Oxide ◽

Two Dimensional ◽

Short Channel ◽

Short Channel Effect ◽

Mos Capacitor ◽

Enhanced Diffusion ◽

Channel Effect ◽

Additional Nitrogen

ABSTRACTExperiment shows that the reverse short channel effect (RSCE) in nMOS devices is critically impacted by the inclusion of nitrogen in the gate oxide. A higher concentration of nitrogen results in a lessened RSCE, i.e. more threshold voltage rolloff for smaller gate lengths. We propose that the additional nitrogen reduces the interstitial recombination rate at the interface, resulting in a smaller interstitial flux and therefore less transient enhanced diffusion (TED) of boron to that interface. To test this hypothesis, we simulate boron redistribution in one and two dimensional MOS capacitor structures, as well as full nMOS devices. We then present simulations calibrated to a 0.2 pim technology currently in production.

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Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect

Electronics Letters ◽

10.1049/el:19950233 ◽

1995 ◽

Vol 31 (5) ◽

pp. 411-412 ◽

Cited By ~ 13

Author(s):

H. Brut ◽

G. Ghibaudo ◽

A. Juge

Keyword(s):

Physical Model ◽

Threshold Voltage ◽

Mos Transistors ◽

Short Channel ◽

Short Channel Effect ◽

Channel Effect

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Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Electronics ◽

10.3390/electronics8010008 ◽

2018 ◽

Vol 8 (1) ◽

pp. 8 ◽

Cited By ~ 1

Author(s):

Young Kim ◽

Jin Lee ◽

Geon Kim ◽

Taesik Park ◽

Hui Kim ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Channel Length ◽

Subthreshold Slope ◽

Access Memory ◽

Short Channel ◽

Short Channel Effect ◽

Channel Effect ◽

Saddle Type ◽

Partial Isolation

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and Ioff characteristics as gate channel length decreased.

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