scholarly journals Smartphone Camera-Based Optical Wireless Communication System: Requirements and Implementation Challenges

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 913 ◽  
Author(s):  
Md. Shahjalal ◽  
Moh. Khalid Hasan ◽  
Mostafa Zaman Chowdhury ◽  
Yeong Min Jang
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Point Of View ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
System Capacity ◽  
Implementation Challenges ◽  
System Requirements ◽  
Implementation Complexities ◽  
User Friendly ◽  
Low Frame Rate

Visible light and infrared bands of the optical spectrum used for optical camera communication (OCC) are becoming a promising technology nowadays. Researchers are proposing new OCC-based architectures and applications in both indoor and outdoor systems using the embedded cameras on smartphones, with a view to making them user-friendly. Smartphones have useful features for developing applications using the complementary metal-oxide-semiconductor cameras, which can receive data from optical transmitters. However, several challenges have arisen in increasing the capacity and communication range, owing to the limitations of current cameras and implementation complexities. In this paper, we provide a comprehensive analysis of the OCC technology requirements and opportunities using smartphone cameras from an implementation point of view. Furthermore, we demonstrate an OCC system using a low frame rate smartphone camera to particularly analyze the requirements and critical implementation challenges. Also, some possible solutions are provided with a view to improving the overall system capacity, communication distance, and stability.

scholarly journals A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1046
Author(s):  
Chuangze Li ◽  
Benguang Han ◽  
Jie He ◽  
Zhongjie Guo ◽  
Longsheng Wu
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Ramp Generator ◽  
Fully Differential ◽  
Generator Circuit ◽  
Pattern Noise ◽  
Fixed Pattern Noise

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

Optimized Post-CMP and Pre-Epi Cleans to Enable Smooth and High Quality Epitaxial Strained Ge Growth on SiGe Strain Relaxed Buffers

2012 ◽  
Vol 187 ◽  
pp. 15-18 ◽  
Author(s):  
Roger Loo ◽  
Laurent Souriau ◽  
Patrick Ong ◽  
Karine Kenis ◽  
Jens Rip
Keyword(s):  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Threading Dislocation ◽  
Strained Si ◽  
Current State ◽  
Device Integration ◽  
Threading Dislocation Density ◽  
20 Nm

Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not outperform current state of the art uni-axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi-axially strained Ge grown on top of SiGe Strain Relaxed Buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the post-CMP and pre-epi cleans which are required to obtain contamination free SiGe surfaces to enable defect free strained Ge growth without reoccurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20 nm thick Ge epitaxially grown on top of SiGe Strain Relaxed Buffers with 85% Ge with a surface roughness as low as 1.6 Å (as measured on areas of 10×10 µm2).

scholarly journals Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics

2015 ◽  
Vol 3 (4) ◽  
pp. 20
Author(s):  
Subrata Biswas ◽  
Poly Kundu ◽  
Md. Hasnat Kabir ◽  
Sagir Ahmed ◽  
Md. Moidul Islam
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Optimal Operation ◽  
Bias Current ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Active Pixel Sensor ◽  
High Frame Rate ◽  
Performance Benchmarking ◽  
Active Pixel ◽  
Readout Time

This paper presents a high frame rate capable Active Pixel Sensor (APS) using Carbon Nanotube Field Effect Transistor (CNTFET) instead of Complementary Metal Oxide Semiconductor (CMOS). Conventionally, the design of a single APS circuit is based on three transistors (3T) model. In order to achieve higher frame rate, one extra transistor with a column sensor circuit has been introduced in the proposed design to reduce the readout time. This study also concerns about the effect of transistor sizing, bias current, and moreover, the chiral vector of CNTFET. The power consumption and power delay product (PDP) are also investigated for specific sets of reset and row selector signal. Data for these studies were collected with the help of HSPICE software which were further plotted in OriginPro to analyze the optimal operation point of APS circuit. The bias current was also recorded for the readout transistor which is uniquely introduced in the proposed model for achieving better readout time. Hence, the main focus of this paper is to improve the frame rate by reducing the readout time. Results of the proposed CNTFET APS circuit are compared with the conventional CMOS APS circuit. The performance benchmarking shows that CNTFET APS cell significantly reduces readout time, PDP, and thus can achieve much higher frame rate than that of conventional CMOS APS cell.

scholarly journals Backside-illuminated scientific CMOS detector for soft X-ray resonant scattering and ptychography

2020 ◽  
Vol 27 (6) ◽  
pp. 1577-1589
Author(s):  
Kewin Desjardins ◽  
Kadda Medjoubi ◽  
Maurizio Sacchi ◽  
Horia Popescu ◽  
Roland Gaudemer ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Resonant Scattering ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Spatial Homogeneity ◽  
X Ray ◽  
Radiation Sources ◽  
Recent Developments ◽  
And Performance ◽  
Backside Illuminated

The impressive progress in the performance of synchrotron radiation sources is nowadays driven by the so-called `ultimate storage ring' projects which promise an unprecedented improvement in brightness. Progress on the detector side has not always been at the same pace, especially as far as soft X-ray 2D detectors are concerned. While the most commonly used detectors are still based on microchannel plates or CCD technology, recent developments of CMOS (complementary metal oxide semiconductor)-type detectors will play an ever more important role as 2D detectors in the soft X-ray range. This paper describes the capabilities and performance of a camera equipped with a newly commercialized backside-illuminated scientific CMOS (sCMOS-BSI) sensor, integrated in a vacuum environment, for soft X-ray experiments at synchrotron sources. The 4 Mpixel sensor reaches a frame rate of up to 48 frames s−1 while matching the requirements for X-ray experiments in terms of high-intensity linearity (>98%), good spatial homogeneity (<1%), high charge capacity (up to 80 ke−), and low readout noise (down to 2 e− r.m.s.) and dark current (3 e− per second per pixel). Performance evaluations in the soft X-ray range have been carried out at the METROLOGIE beamline of the SOLEIL synchrotron. The quantum efficiency, spatial resolution (24 line-pairs mm−1), energy resolution (<100 eV) and radiation damage versus the X-ray dose (<600 Gy) have been measured in the energy range from 40 to 2000 eV. In order to illustrate the capabilities of this new sCMOS-BSI sensor, several experiments have been performed at the SEXTANTS and HERMES soft X-ray beamlines of the SOLEIL synchrotron: acquisition of a coherent diffraction pattern from a pinhole at 186 eV, a scattering experiment from a nanostructured Co/Cu multilayer at 767 eV and ptychographic imaging in transmission at 706 eV.

scholarly journals New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 368 ◽  
Author(s):  
Giulia Santoro ◽  
Giovanna Turvani ◽  
Mariagrazia Graziano
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Strong Impact ◽  
Technological Advancement ◽  
Data Movement ◽  
Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

scholarly journals Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1086 ◽  
Author(s):  
Manabu Suzuki ◽  
Yuki Sugama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa
Keyword(s):  
High Speed ◽  
Cooling System ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Photoelectric Conversion ◽  
Memory Array ◽  
Record Length

In this paper, a prototype ultra-high speed global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with pixel-wise trench capacitor memory array achieving over 100 million frames per second (fps) with up to 368 record length by burst correlated double sampling (CDS) operation is presented. Over 100 Mfps high frame rate is obtained by reduction of pixel output load by the pixel-wise memory array architecture and introduction of the burst CDS operation which minimizes the pixel driving pulse transitions. Long record length is realized by high density analog memory integration with Si trench capacitors. A maximum 125 Mfps frame rate with up to 368 record length video capturing was confirmed under room temperature without any cooling system. The photoelectric conversion characteristics of the burst CDS operation were measured and compared with those of the conventional CDS operation.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals The 3D Modeling System for Bioaerosol Distribution Based on Planar Laser-Induced Fluorescence

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2607
Author(s):  
Siying Chen ◽  
Yuanyuan Chen ◽  
Yinchao Zhang ◽  
Pan Guo ◽  
He Chen ◽  
...  
Keyword(s):  
3D Reconstruction ◽  
3D Modeling ◽  
Aerosol Particles ◽  
Laser Induced Fluorescence ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Laser Source ◽  
Confined Space ◽  
Planar Laser Induced Fluorescence ◽  
Planar Laser

Although it is quite challenging to image and analyze the spatial distribution of bioaerosols in a confined space, a three-dimensional (3D) modeling system based on the planar laser-induced fluorescence (PLIF) technique is proposed in this paper, which is designed to analyze the temporal and spatial variations of bioaerosol particles in a confined chamber. The system employs a continuous planar laser source to excite the fluoresce, and a scientific complementary metal oxide semiconductor (sCMOS) camera to capture images of 2048 × 2048 pixels at a frame rate of 12 Hz. While a sliding platform is moving back and forth on the track, a set of images are captured at different positions for 3D reconstruction. In this system, the 3D reconstruction is limited to a maximum measurement volume of about 50 cm × 29.7 cm × 42 cm, with a spatial resolution of about 0.58 mm × 0.82 mm × 8.33 mm, and a temporal resolution of 5 s. Experiments were carried out to detect the PLIF signals from fluorescein aerosols in the chamber, and then 3D reconstruction was used to visualize and analyze the diffusion of aerosol particles. The results prove that the system can be applied to clearly reconstruct the 3D distribution and record the diffusion process of aerosol particles in a confined space.

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