scholarly journals Effects of the Target on the Performance of an Ultra-Low Power Eddy Current Displacement Sensor for Industrial Applications

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1287
Author(s):  
Alessandro Bertacchini ◽  
Marco Lasagni ◽  
Gabriele Sereni
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Eddy Current ◽  
Supply Voltage ◽  
Low Cost ◽  
Industrial Applications ◽  
Complete Characterization ◽  
Displacement Sensor ◽  
Ultra Low Power ◽  
Industry Automation

The demand for smart, low-power, and low-cost sensors is rapidly increasing with the proliferation of industry automation. In this context, an Ultra-Low Power Eddy Current Displacement Sensor (ULP-ECDS) targeting common industrial applications and designed to be embedded in wireless Industrial Internet of Things (IIoT) devices is presented. A complete characterization of the realized ULP-ECDS operating with different metallic targets was carried out. The choice of the considered targets in terms of material and thickness was inspired by typical industrial scenarios. The experimental results show that the realized prototype works properly with extremely low supply voltages, allowing for obtaining an ultra-low power consumption, significantly lower than other state-of-the-art solutions. In particular, the proposed sensor reached the best resolution of 2 µm in case of a carbon steel target when operated with a supply voltage of 200 mV and with a power consumption of 150 µW. By accepting a resolution of 12 µm, it is possible to further reduce the power consumption of the sensor to less than 10 µW. The obtained results also demonstrate how the performances of the sensor are strongly dependent on both the target and the demodulation technique used to extract the displacement information. This allowed for defining some practical guidelines that can help the design of effective solutions considering application-specific constraints.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

Intelligent Logistics Monitoring Microsystem Based on STM32

2015 ◽  
Vol 645-646 ◽  
pp. 896-899 ◽  
Author(s):  
Feng Wang ◽  
Wen Zhong Lou ◽  
Ming Ru Guo ◽  
Yu Fei Lu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Humidity Sensor ◽  
Low Cost ◽  
Low Power Consumption ◽  
Sleep Mode ◽  
Acceleration Sensor ◽  
Ultra Low Power ◽  
Intelligent Logistics ◽  
Data Acquisition Module

A intelligent logistics monitoring microsystem has been designed based on STM32F103T8, which is high ability, low power consumption and low cost. The radio frequency (RF) chip CC1101, the acceleration sensor BMA280 and the temperature and humidity sensor HTU21D are selected to acquire the corresponding data for the intelligent logistics microsystem, which are ultra-low power consumption and ultra-small size. Moreover, in order to further reduce power consumption, the interrupt mode is adopted in the data acquisition module and the sleep mode is used in the MCU module in the software control. On the other hand, in order to further optimize the performance of miniaturization, the SWD (Serial Wire Debug) protocol is used. Meanwhile, the system will alarm the transportation officer once the acquired data met or exceed the threshold, which will help him to take corresponding measures timely, thus reducing the risk of occurrence effectively.

scholarly journals Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

2020 ◽  
Vol 9 (1) ◽  
pp. 396-402
Author(s):  
S. A. Z. Murad ◽  
A. Azizan ◽  
A. F. Hasan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Return Loss ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wireless Sensor ◽  
Total Power ◽  
Ultra Low Power ◽  
Noise Amplifier

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

scholarly journals A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Simulation Analysis ◽  
Supply Voltage ◽  
High Gain ◽  
Common Mode ◽  
Ultra Low Power ◽  
The Common

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

A ± 0.2 V, 0.12 μW CCTA USING VTMOS AND AN APPLICATION FRACTIONAL-ORDER UNIVERSAL FILTER

2014 ◽  
Vol 23 (09) ◽  
pp. 1450126 ◽  
Author(s):  
TADA COMEDANG ◽  
PATTNA INTANI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Fractional Order ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Ultra Low Power ◽  
Variable Threshold ◽  
High Output Impedance

In this paper, a variable threshold voltage metal oxide semiconductor (VTMOS) field effect transistor is used to improve an ultra-low voltage, ultra-low power current conveyor transconductance amplifier (CCTA). To achieve the desired result, an analytical subthreshold VTMOS model is used. Designs that utilize the TSMC 0.18 μm technology are verified using PSPICE simulation. The power consumption is simply 0.12 μW at a ± 0.2 V supply voltage. The proposed CCTA is synthesized using fractional-order (FO) universal filters that can simultaneously realise low pass (LP), high pass (HP) and bandpass (BP) responses with independent control of quality factor and pole frequency by transconductances (gm). Moreover, the circuit has low input and high output impedance which would be an ideal choice for cascading in current-mode circuit. The FO filters are constructed using two FO capacitors of orders α and β (0 < α, β ≤ 1). The FO filters provide improved performance in terms of pole frequency compared with conventional-order filters. The filter has a low power consumption of 0.71 μW at a ± 0.2 V supply voltage. The validity of the proposed filter is verified through PSPICE simulations.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power
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