Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals Effects of the Target on the Performance of an Ultra-Low Power Eddy Current Displacement Sensor for Industrial Applications

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1287
Author(s):  
Alessandro Bertacchini ◽  
Marco Lasagni ◽  
Gabriele Sereni
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Eddy Current ◽  
Supply Voltage ◽  
Low Cost ◽  
Industrial Applications ◽  
Complete Characterization ◽  
Displacement Sensor ◽  
Ultra Low Power ◽  
Industry Automation

The demand for smart, low-power, and low-cost sensors is rapidly increasing with the proliferation of industry automation. In this context, an Ultra-Low Power Eddy Current Displacement Sensor (ULP-ECDS) targeting common industrial applications and designed to be embedded in wireless Industrial Internet of Things (IIoT) devices is presented. A complete characterization of the realized ULP-ECDS operating with different metallic targets was carried out. The choice of the considered targets in terms of material and thickness was inspired by typical industrial scenarios. The experimental results show that the realized prototype works properly with extremely low supply voltages, allowing for obtaining an ultra-low power consumption, significantly lower than other state-of-the-art solutions. In particular, the proposed sensor reached the best resolution of 2 µm in case of a carbon steel target when operated with a supply voltage of 200 mV and with a power consumption of 150 µW. By accepting a resolution of 12 µm, it is possible to further reduce the power consumption of the sensor to less than 10 µW. The obtained results also demonstrate how the performances of the sensor are strongly dependent on both the target and the demodulation technique used to extract the displacement information. This allowed for defining some practical guidelines that can help the design of effective solutions considering application-specific constraints.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

scholarly journals Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

2021 ◽  
Vol 15 ◽  
Author(s):  
Pavan Kumar Chundi ◽  
Dewei Wang ◽  
Sung Justin Kim ◽  
Minhao Yang ◽  
Joao Pedro Cerqueira ◽  
...  
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
State Of The Art ◽  
Spiking Neural Network ◽  
Power Gating ◽  
Ultra Low Power ◽  
Fine Grained ◽  
Input Activity

This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power dissipation. A key observation is that the input signal to always-on hardware is typically sparse in time. This is a great opportunity that a SNN classifier can leverage because the switching activity and the power consumption of SNN hardware can scale with spike rate. To leverage this scalability, the proposed SNN classifier architecture employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. The prototype is fabricated in 65 nm CMOS and occupies an area of 1.99 mm2. At 0.52 V supply voltage, it consumes 75 nW at no input activity and less than 300 nW at 100% input activity. It still maintains competitive inference accuracy for KWS and other always-on classification workloads. The prototype achieved a power consumption reduction of over three orders of magnitude compared to the state-of-the-art for SNN hardware and of about 2.3X compared to the state-of-the-art KWS hardware.

An Ultra-Low-Power Five-Input Majority Gate in Quantum-Dot Cellular Automata

2020 ◽  
Vol 29 (11) ◽  
pp. 2050176
Author(s):  
Feifei Deng ◽  
Guangjun Xie ◽  
Shaowei Wang ◽  
Xin Cheng ◽  
Yongqiang Zhang
Keyword(s):  
Cellular Automata ◽  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Single Layer ◽  
Full Adder ◽  
Majority Gate ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Number Of Cells

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.

scholarly journals A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

2019 ◽  
Vol 8 (3) ◽  
pp. 162
Author(s):  
Pritty Pritty ◽  
Manoj Kumar ◽  
Mariyam Zunairah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Full Adder ◽  
Digital Circuit ◽  
Xor Gate ◽  
Digital Circuit Design ◽  
Result Show ◽  
Body Bias

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

scholarly journals Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

2020 ◽  
Vol 9 (1) ◽  
pp. 396-402
Author(s):  
S. A. Z. Murad ◽  
A. Azizan ◽  
A. F. Hasan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Return Loss ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wireless Sensor ◽  
Total Power ◽  
Ultra Low Power ◽  
Noise Amplifier

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

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