A ± 0.2 V, 0.12 μW CCTA USING VTMOS AND AN APPLICATION FRACTIONAL-ORDER UNIVERSAL FILTER

2014 ◽  
Vol 23 (09) ◽  
pp. 1450126 ◽  
Author(s):  
TADA COMEDANG ◽  
PATTNA INTANI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Fractional Order ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Ultra Low Power ◽  
Variable Threshold ◽  
High Output Impedance

In this paper, a variable threshold voltage metal oxide semiconductor (VTMOS) field effect transistor is used to improve an ultra-low voltage, ultra-low power current conveyor transconductance amplifier (CCTA). To achieve the desired result, an analytical subthreshold VTMOS model is used. Designs that utilize the TSMC 0.18 μm technology are verified using PSPICE simulation. The power consumption is simply 0.12 μW at a ± 0.2 V supply voltage. The proposed CCTA is synthesized using fractional-order (FO) universal filters that can simultaneously realise low pass (LP), high pass (HP) and bandpass (BP) responses with independent control of quality factor and pole frequency by transconductances (gm). Moreover, the circuit has low input and high output impedance which would be an ideal choice for cascading in current-mode circuit. The FO filters are constructed using two FO capacitors of orders α and β (0 < α, β ≤ 1). The FO filters provide improved performance in terms of pole frequency compared with conventional-order filters. The filter has a low power consumption of 0.71 μW at a ± 0.2 V supply voltage. The validity of the proposed filter is verified through PSPICE simulations.

Challenges and Limitations of Low Power Techniques

2016 ◽  
pp. 48-70
Author(s):  
Vandana B. ◽  
Patro B. S.
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Semiconductor Device ◽  
Low Voltage ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Gate Length ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Contemporary World

In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.

scholarly journals A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Simulation Analysis ◽  
Supply Voltage ◽  
High Gain ◽  
Common Mode ◽  
Ultra Low Power ◽  
The Common

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

scholarly journals Effects of the Target on the Performance of an Ultra-Low Power Eddy Current Displacement Sensor for Industrial Applications

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1287
Author(s):  
Alessandro Bertacchini ◽  
Marco Lasagni ◽  
Gabriele Sereni
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Eddy Current ◽  
Supply Voltage ◽  
Low Cost ◽  
Industrial Applications ◽  
Complete Characterization ◽  
Displacement Sensor ◽  
Ultra Low Power ◽  
Industry Automation

The demand for smart, low-power, and low-cost sensors is rapidly increasing with the proliferation of industry automation. In this context, an Ultra-Low Power Eddy Current Displacement Sensor (ULP-ECDS) targeting common industrial applications and designed to be embedded in wireless Industrial Internet of Things (IIoT) devices is presented. A complete characterization of the realized ULP-ECDS operating with different metallic targets was carried out. The choice of the considered targets in terms of material and thickness was inspired by typical industrial scenarios. The experimental results show that the realized prototype works properly with extremely low supply voltages, allowing for obtaining an ultra-low power consumption, significantly lower than other state-of-the-art solutions. In particular, the proposed sensor reached the best resolution of 2 µm in case of a carbon steel target when operated with a supply voltage of 200 mV and with a power consumption of 150 µW. By accepting a resolution of 12 µm, it is possible to further reduce the power consumption of the sensor to less than 10 µW. The obtained results also demonstrate how the performances of the sensor are strongly dependent on both the target and the demodulation technique used to extract the displacement information. This allowed for defining some practical guidelines that can help the design of effective solutions considering application-specific constraints.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

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