scholarly journals Reduced-Reflection Multilayer PCB Microstrip with Discontinuity Characterization

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1473
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdenas
Keyword(s):  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Academic Research ◽  
System Level ◽  
Reference Plane ◽  
Impedance Change ◽  
Circuit Boards ◽  
Impedance Mismatch ◽  
The Difference ◽  
Technology And Communication

In the era of technology and communication, printed circuit boards (PCBs) can be found in a myriad of devices—from ordinary household items, to state of the art custom metrology equipment. Different types of component for wireless communications are available and come in various packages, supplied by multiple manufacturers. The signal landpads for some high-frequency connectors and components, encapsulated in larger packages, are usually wider than the controlled impedance trace, thereby introducing unwanted impedance mismatch and resulting in signal reflections. The component land pad and microstrip width a discrepancy issue can be found in both complex high-density industrial devices and system-level academic research papers. This paper addresses the topic of compensating discontinuities, introduced by signal pads, which are wider than the target impedance microstrip, characterizes the difference between the compensated and uncompensated microstrip with discontinuity, and proposes a generalized guideline on compensating for the introduced impedance change in multilayer PCBs. The compensation method is based upon carefully designing the stackup of the PCB allowing for a reference plane cutout under the discontinuity to even out the impedance mismatch. A 6-layer PCB with IT180A dielectric material containing three structures has been manufactured and characterized using an Agilent E8363B vector network analyzer (VNA). A 4–12 dB improvement in S11 response in the whole frequency range up to 10 GHz, compared to that when no compensation has been applied, was observed.

Fast Precise Positioning of Circular Mark in Automatic Optical Inspection

2013 ◽  
Vol 325-326 ◽  
pp. 1614-1618
Author(s):  
Guang Jie Xiong ◽  
Yu Fei Liu ◽  
Rui Zhen Liu
Keyword(s):  
Printed Circuit Boards ◽  
Positioning Error ◽  
Circuit Boards ◽  
Precise Positioning ◽  
Automatic Optical Inspection ◽  
Running Time ◽  
Printed Circuit ◽  
Optical Inspection ◽  
Positioning Method ◽  
The Difference

Captured circular marks are deformed sometimes when Automatic Optical Inspection (AOI) is used to detect various defects on Printed Circuit Boards (PCB), which may affect the precision of inspection. A new accurate positioning method of circular marks is proposed to solve the problem by obtaining the center of the most round ellipse based on the criterion that the ratio of the difference between the length and width of its circumscribed rectangle and the width of the rectangle is less than 0.1. The simulation tests show that, if the mark has much more deformations, the center positioning error of the proposed algorithm is about 0.013 pixels, and the running time is less than 40ms. Therefore, the proposed method provides good characteristics such as speediness, strong anti-interference ability and robustness.

Modeling Melting Solder in System-in-Package Assembly

2005 ◽  
Author(s):  
J. F. Zhao ◽  
J. F. Wang ◽  
C. Yang
Keyword(s):  
Finite Element ◽  
Stress Field ◽  
Solder Joint ◽  
Printed Circuit Boards ◽  
Element Model ◽  
System Level ◽  
Electrical Performance ◽  
Superposition Method ◽  
Circuit Boards ◽  
Passive Components

System-in-package (SiP) technologies typically demand an increasing number of passive components assembled into a single package to achieve system level electrical performance. Traditionally, these passive components and their assembly technologies are designed for printed circuit boards and are now integrated at the package level. However, problems may arise when solder joints are used as interconnects between the passive components and the substrate in SiP system. The solder joint may melt during the surface mounting process. Since the size of the solder joint is comparable to that of the passive components, the melting may significantly alter the stress field in the package. Consequent failure may occur if the interconnect structure is not properly designed. It is a challenge to simulate solder melting with commercial finite element codes. In this paper, the interaction between the melting solder and the surrounding structures is investigated. The stress superposition method is used in the finite element model, in which the melting solder is removed from the package and a void with identical geometry was analyzed in its place. The overall stress field is the superposition of the stress field due to temperature change and the stress field caused by the uniform pressure acting on the void surface. This method greatly simplifies the mechanical modeling.

A System Level Thermal Analysis of Large Telecommunication Racks

2003 ◽  
Author(s):  
L. T. Yeh
Keyword(s):  
Thermal Analysis ◽  
Flow Rate ◽  
Printed Circuit Boards ◽  
System Level ◽  
Circuit Boards ◽  
Air Flow Rate ◽  
Printed Circuit ◽  
Computational Fluid Dynamics Cfd ◽  
Cfd Method ◽  
Level Analysis

A system level thermal analysis is performed by employing the computational fluid dynamics (CFD) method on a large telecommunication rack. Each rack consists of two identical shelves located on the top-to-bottom orientation. Each shelf includes one fan tray with 6 fans, 3 card cages with a total of 50 printed circuit boards (PCBs). Air enters from the front of the shelf, and then makes a 90-degree turn upwards through PCBs, and finally turns another 90-degree to exit the system from the back of the shelf. The system level analysis is performed independently on each shelf. The main purpose of the analysis is to determine the air flow rate to individual printed circuit boards as well as the air temperature distribution in the system. The computed flow rate for individual PCBs is then used for a detailed board analysis to predict the component temperatures of individual boards.

Successful Practices for the Modeling of Printed Circuit Boards and Substrates Using Electromagnetic Field Solvers

2010 ◽  
Vol 2010 (1) ◽  
pp. 000413-000421 ◽  
Author(s):  
Steven G. Pytel ◽  
Scott C. McMorrow ◽  
Tom Dagostino ◽  
Sergey Polstyanko ◽  
Werner Thiel ◽  
...  
Keyword(s):  
Electromagnetic Field ◽  
High Speed ◽  
Printed Circuit Boards ◽  
Boundary Element Methods ◽  
System Level ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Circuit Simulator ◽  
Reference Design ◽  
Electromagnetic Field Solvers

The aim of this work is to provide strategies for creating highly accurate models of printed circuit boards (PCBs) and substrates using electromagnetic field solvers. It will examine how to choose the correct field solver for a particular application from among full-wave, modal decomposition, finite element and boundary element methods. Tradeoffs between time and accuracy of the different solvers will be discussed. The focus is on model creation for use in time domain circuit simulators, but analysis of the frequency domain data will be used to correlate measurement to simulation. The problem of correlating simulation results with measurements is also discussed. A physical layer reference design (PLRD) board has been constructed, measured and simulated with the various field solvers. The results are analyzed to understand why differences occur between simulation and measured data. The impacts of these differences on system-level simulations of high-speed serial links are studied using a circuit simulator.

Boundary-Scan’s Next Plateau: Testing and In-System Configuration at the System Level

2002 ◽  
Author(s):  
Pete Collins ◽  
Ray Dellecker
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
System Level ◽  
Boundary Scan ◽  
Circuit Boards ◽  
System Configuration ◽  
Production Lines ◽  
Physical Test ◽  
Dynamic Verification ◽  
Electronic Assemblies

Abstract Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.

Effect of RCC on the Reliability of Adhesive Flip Chip Joints

2006 ◽  
Vol 129 (3) ◽  
pp. 260-265 ◽  
Author(s):  
Laura K. Frisk ◽  
Kati H. Kokko
Keyword(s):  
Flip Chip ◽  
Printed Circuit Boards ◽  
Coefficient Of Thermal Expansion ◽  
Temperature Cycling ◽  
Circuit Boards ◽  
Adhesive Film ◽  
The Difference ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Conductive Particles

A need for higher packaging density and functionality has increased the use of new packaging technologies, which has also caused demand for higher interconnect densities on printed circuit boards (PCBs). Sequential build-up (SBU) processes can be used to meet these demands. In the SBU process, additional dielectric and conductor layers are formed on a core board, which is typically made of FR-4. Microvias are formed on these layers to achieve an electrical connection between them and the core board. Resin-coated copper foil (RCC) is the most widely used dielectric layer in the SBU process. The effect of RCC on the reliability of flip chip joints with anisotropically conductive adhesive film (ACF) was studied. Two substrates were used. The difference between the substrates was RCC laminated on the other substrate. The reliability of the test samples was studied using a temperature cycling test and a constant humidity test. The reliability of the substrate with the RCC was found to be better in both tests. Failure mechanisms were studied after the tests, using optical and scanning electron microscopes. After the temperature cycling, several of the test samples made with two highest bonding pressures showed delamination, which has probably caused the failures. In addition, failures occurred during the changes in the test temperature. These were probably caused by warping of the flip chip package. No delamination was found in the test samples with the lowest pressure. The failures in these series were probably caused by relaxation of the adhesive matrix and by too low deformation of the conductive particles. Several cracks had formed on the FR-4 substrates without the RCC during the temperature cycling. In addition, air bubbles were found in the test samples with the FR-4 substrates without the RCC. Since RCC is a pure resin system, it has a high coefficient of thermal expansion, which may cause problems, especially when large components are attached to it. However, in this study, the RCC was found to increase the reliability of the flip chip joints made with ACF during both temperature cycling and constant humidity testing.

Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations

2016 ◽  
Vol 138 (2) ◽  
Author(s):  
M. Baris Dogruoz
Keyword(s):  
Thermal Conductivity ◽  
Temperature Distribution ◽  
Joule Heating ◽  
Computer Aided Design ◽  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Circuit Board ◽  
System Level ◽  
Cfd Simulations ◽  
Printed Circuit

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

Modeling of Resin Flow in Reinforced Dielectric Prepregs

2008 ◽  
Vol 130 (2) ◽  
Author(s):  
Pavel Simacek ◽  
Suresh G. Advani ◽  
Kossi Zonvide ◽  
Leonard W. Barrett
Keyword(s):  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Applied Pressure ◽  
Processing Parameters ◽  
Circuit Board ◽  
Resin Flow ◽  
Circuit Boards ◽  
Typical Material ◽  
Lamination Process ◽  
Closing Rate

Manufacturing of printed circuit boards or chip-packaging substrates involves the use of resin-filled reinforcement materials, known as prepregs, to bond together laminates with patterned copper layers and serve as dielectric material. In the circuit board or substrate lamination process, the prepreg sheet is placed on top of the conductive copper patterns and pressure is applied to squeeze the resin out of the prepreg to flow and fill the gaps between the baseboard and the copper as well as drilled holes and vias. The primary processing requirement is for resin to fill all the gaps within reasonable time and pressure limits, before the resin cures to a hardened thermoset material. As the resin flow path may be nontrivial, it is desirable to model resin flow and filling of the gap as a function of applied pressure and lamination press closing rate so that one can successfully manufacture a variety of circuit board designs with different material systems. In this work, we model the flow during the filling of the gaps and justify noteworthy simplifications to provide a solution in closed form. This allows us to relate the material and process parameters such as prepreg thickness and applied pressure to the circuit board design. It also permits prediction of the transient development of gap filling. We illustrate the factors that influence the flow and fill process and discuss their importance. Finally, we analyze the process with typical material and processing parameters and compare it with laboratory scale and industrial experiments.

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