scholarly journals A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 584
Author(s):  
Su-in Yi ◽  
Jungsik Kim

Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.


Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.


Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.


Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 829
Author(s):  
Taejin Jang ◽  
Suhyeon Kim ◽  
Jeesoo Chang ◽  
Kyung Kyu Min ◽  
Sungmin Hwang ◽  
...  

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.


2011 ◽  
Vol 50 (4S) ◽  
pp. 04DD08
Author(s):  
Wandong Kim ◽  
Dae Woong Kwon ◽  
Jung Hwan Ji ◽  
Jung Hoon Lee ◽  
Jong-Ho Lee ◽  
...  

2020 ◽  
Vol 29 (3) ◽  
pp. 038501
Author(s):  
He-Kun Zhang ◽  
Xuan Tian ◽  
Jun-Peng He ◽  
Zhe Song ◽  
Qian-Qian Yu ◽  
...  

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