scholarly journals A Bipolar ±13 mV Self-Starting and 85% Peak Efficiency DC/DC Converter for Thermoelectric Energy Harvesting

Energies ◽  
2020 ◽  
Vol 13 (20) ◽  
pp. 5501
Author(s):  
Harald Dillersberger ◽  
Bernd Deutschmann ◽  
Douglas Tham

This paper presents a novel converter for boosting the low-voltage output of thermoelectric energy harvesters to power standard electronic circuits. The converter can start up from a fully depleted state of the system off a bipolar ±13 mV input and can boost it to output voltages of up to 5 V. The converter comprises two transformers, one for each polarity that are multiplexed between an oscillator (used during startup) and a flyback converter (used during normal operation). To eliminate leakage currents in the input stage, the unused converter is completely turned off at startup and both converters are automatically shut off if the input power is found to be too low. Measurement results of the converter designed in a 180 nm CMOS process demonstrate a peak end-to-end conversion efficiency of 85% and nearly perfect impedance matching over the full input voltage range. This is the first time that a converter for ultra-low bipolar input voltages achieves the same performance as a unipolar converter.

2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1391
Author(s):  
Zushuai Xie ◽  
Zhiqiang Wu ◽  
Jianhui Wu

This paper presents a voltage level shifter (VLS) based on two feedback loops. The complementary feedback signals in the high voltage domain are re-used to assist voltage conversion and the complementary phase in the low voltage domain is not required. Unlike the conventional VLS, which depends on the pull-up network and pull-down network to achieve level shift, the transitions of both high-to-low and low-to-high of the proposed VLS are undertaken by two different feedback loops, respectively. Implemented in a standard 180 nm CMOS process, post-layout Monte Carlo (MC) simulations from 4000 points under mismatch variation show that the dynamic power (DP) and the propagation delay (PD) of the proposed VLS are 105.3 nW and 2.0 ns, respectively, at an input voltage VIN = 0.4 V with input frequency fin = 0.1 MHz. Meanwhile, the excellent normalized standard deviation of DP and PD is obtained with the proposed scheme. The temperature range for normal operation is from −20 °C to 85 °C.


Author(s):  
Hal Edwards ◽  
Jeff Debord ◽  
Toan Tran ◽  
Dave Freeman ◽  
Kenneth Maggio

This chapter presents a study of thermoelectric energy harvesting with nano-sized thermopiles (nTE) in a planar 65 nm silicon CMOS process. These devices generated power from a 5C temperature difference at a density comparable to commercially available thermoelectric generators, following a metric used in the research literature (Hudak, 2008). By analyzing these devices as a thermoelectric harvesting system, the authors explore the impact of additional performance metrics such as heat source/sink thermal impedance, available heat flow density, and voltage stacking, providing a more comprehensive set of criteria for evaluating the suitability of a thermal harvesting technology. The authors use their thermoelectric system theory to consider the prospects for several thermoelectric energy harvesting applications.


2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.


Energies ◽  
2020 ◽  
Vol 13 (4) ◽  
pp. 863 ◽  
Author(s):  
Jaeil Baek ◽  
Han-Shin Youn

This paper presents a full-bridge active-clamp forward-flyback (FBACFF) converter with an integrated transformer sharing a single primary winding. Compared to the conventional active-clamp-forward (ACF) converter, the proposed converter has low voltage stress on the primary switches due to its full-bridge active-clamp structure, which can leverage high performance Silicon- metal–oxide–semiconductor field-effect transistor (Si-MOSFET) of low voltage rating and low channel resistance. Integrating forward and flyback operations allows the proposed converter to have much lower primary root mean square (RMS) current than the conventional phase-shifted-full-bridge (PSFB) converter, while covering wide input/output voltage range with duty ratio over 0.5. The proposed integrated transformer reduces the transformer conduction loss and simplify the secondary structure of the proposed converter. As a result, the proposed converter has several advantages: (1) high heavy load efficiency, (2) wide input voltage range operation, (3) high power density with the integrated transformer, and (4) low cost. The proposed converter is a very promising candidate for applications with wide input voltage range and high power, such as the low-voltage DC (LDC) converter for eco-friendly vehicles.


2013 ◽  
Vol 772 ◽  
pp. 731-734
Author(s):  
Shi Zhong Guo ◽  
Kai Xie ◽  
Ying Hao Ye ◽  
Xiao Ping Li

This paper presents a ultra low voltage resonant converter for thermoelectric energy harvesting.A key challenge in designing energy harvesting system is that thermoelectric generators output a very low voltage (-0.3V~0.3V). Therefore, a power converter is used to boost the output voltage of the energy transducer and transfer energy into an energy buffer for storage. The converter operates from input voltages ranging from-500mV to-60mV and 60mV to 500mV while supplying a 4.2 V DC output. The converter consumes 88μW of quiescent power, delivers up to 1.6 (1.8) mW of output power, and is 65(67)% efficient for a-100mV and 100mV input, respectively.


Author(s):  
Jim Hui Yap ◽  
Yan Chiew Wong

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster.


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