scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

2014 ◽  
Vol 543-547 ◽  
pp. 800-805 ◽  
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Ming Hui Fan ◽  
Yu Sen Xu ◽  
Guo Lin Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Settling Time ◽  
Voltage Range ◽  
Class Ab ◽  
Response Enhancement ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Ldo Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications

2019 ◽  
Vol 28 (03) ◽  
pp. 1950043 ◽  
Author(s):  
M. Jahangiri ◽  
A. Farrokhi
Keyword(s):  
Output Voltage ◽  
Input Voltage ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Wide Range ◽  
Unity Gain ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Voltage Spike

A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50[Formula: see text]mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The output voltage of the LDO was set to 1.2[Formula: see text]V for an input voltage of 1.4–2[Formula: see text]V. The Simulation results verify that the transient times are less than 2.8[Formula: see text][Formula: see text]s and the maximum undershoot and overshoot are 20[Formula: see text]mV while consuming only 26[Formula: see text][Formula: see text]A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100[Formula: see text]PF.

scholarly journals A Bipolar ±13 mV Self-Starting and 85% Peak Efficiency DC/DC Converter for Thermoelectric Energy Harvesting

Energies ◽  
2020 ◽  
Vol 13 (20) ◽  
pp. 5501
Author(s):  
Harald Dillersberger ◽  
Bernd Deutschmann ◽  
Douglas Tham
Keyword(s):  
Low Voltage ◽  
Impedance Matching ◽  
Input Voltage ◽  
Input Power ◽  
Normal Operation ◽  
Cmos Process ◽  
Fully Depleted ◽  
Voltage Range ◽  
Thermoelectric Energy ◽  
Thermoelectric Energy Harvesting

This paper presents a novel converter for boosting the low-voltage output of thermoelectric energy harvesters to power standard electronic circuits. The converter can start up from a fully depleted state of the system off a bipolar ±13 mV input and can boost it to output voltages of up to 5 V. The converter comprises two transformers, one for each polarity that are multiplexed between an oscillator (used during startup) and a flyback converter (used during normal operation). To eliminate leakage currents in the input stage, the unused converter is completely turned off at startup and both converters are automatically shut off if the input power is found to be too low. Measurement results of the converter designed in a 180 nm CMOS process demonstrate a peak end-to-end conversion efficiency of 85% and nearly perfect impedance matching over the full input voltage range. This is the first time that a converter for ultra-low bipolar input voltages achieves the same performance as a unipolar converter.

A 2 × VDD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850143
Author(s):  
Shuangxing Zhao ◽  
Chenchang Zhan ◽  
Guigang Cai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
System On Chip ◽  
Cmos Process ◽  
Fast Transient Response ◽  
Power Transistors ◽  
Fast Transient ◽  
On Chip ◽  
Output Capacitor ◽  
Ldo Regulator

This paper presents a [Formula: see text]-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-[Formula: see text] supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate [Formula: see text] voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-[Formula: see text]m CMOS process which achieves 3.3–3.6[Formula: see text]V nominal input, 3.1[Formula: see text]V nominal output and 100[Formula: see text]mA loading capability with all the transistors being 1.8[Formula: see text]V MOSFETs.

scholarly journals A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 146
Author(s):  
Young-Joe Choe ◽  
Hyohyun Nam ◽  
Jung-Dong Park
Keyword(s):  
Maximum Load ◽  
Input Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Feed Forward ◽  
Power Supply Rejection Ratio ◽  
Wide Range ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Ripple Cancellation

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN
Keyword(s):  
Relative Error ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Experimental Result ◽  
Voltage Range ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Power Dispersion ◽  
Four Quadrant

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

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