Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

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Extreme Energy Efficiency by Near Threshold Voltage Operation

Near Threshold Computing ◽

10.1007/978-3-319-23389-5_1 ◽

2016 ◽

pp. 3-18 ◽

Cited By ~ 3

Author(s):

Shekhar Borkar

Keyword(s):

Energy Efficiency ◽

Threshold Voltage ◽

Near Threshold

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Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Electronics ◽

10.3390/electronics8060611 ◽

2019 ◽

Vol 8 (6) ◽

pp. 611 ◽

Cited By ~ 1

Author(s):

Ik Joon Chang ◽

Yesung Kang ◽

Youngmin Kim

Keyword(s):

Threshold Voltage ◽

Supply Voltage ◽

Random Access ◽

Channel Length ◽

Voltage Level ◽

Exact Data ◽

Optimum Energy ◽

The Stability ◽

20 Nm ◽

Near Threshold

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

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Low-power design towards implantable neural signal processor- energy efficiency analysis for near-threshold voltage circuits design

2015 International Symposium on Bioelectronics and Bioinformatics (ISBB) ◽

10.1109/isbb.2015.7344957 ◽

2015 ◽

Author(s):

I-Chyn Wey ◽

Jia-Feng Huang ◽

Cihun-Siyong Alex Gong ◽

Shiang-Wei Li ◽

Chang-Chieh Lin ◽

...

Keyword(s):

Energy Efficiency ◽

Low Power ◽

Threshold Voltage ◽

Low Power Design ◽

Efficiency Analysis ◽

Neural Signal ◽

Energy Efficiency Analysis ◽

Signal Processor ◽

Near Threshold

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Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data Paths

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea10040042 ◽

2020 ◽

Vol 10 (4) ◽

pp. 42

Author(s):

Mehdi Tahoori ◽

Mohammad Saber Golanbari

Keyword(s):

Energy Efficiency ◽

Performance Optimization ◽

Supply Voltage ◽

Cross Layer ◽

Improve Energy Efficiency ◽

Threshold Data ◽

Order Of Magnitude ◽

Improved Performance ◽

And Performance ◽

Near Threshold

Modern electronic devices are an indispensable part of our everyday life. A major enabler for such integration is the exponential increase of the computation capabilities as well as the drastic improvement in the energy efficiency over the last 50 years, commonly known as Moore’s law. In this regard, the demand for energy-efficient digital circuits, especially for application domains such as the Internet of Things (IoT), has faced an enormous growth. Since the power consumption of a circuit highly depends on the supply voltage, aggressive supply voltage scaling to the near-threshold voltage region, also known as Near-Threshold Computing (NTC), is an effective way of increasing the energy efficiency of a circuit by an order of magnitude. However, NTC comes with specific challenges with respect to performance and reliability, which mandates new sets of design techniques to fully harness its potential. While techniques merely focused at one abstraction level, in particular circuit-level design, can have limited benefits, cross-layer approaches result in far better optimizations. This paper presents instruction multi-cycling and functional unit partitioning methods to improve energy efficiency and resiliency of functional units. The proposed methods significantly improve the circuit timing, and at the same time considerably limit leakage energy, by employing a combination of cross-layer techniques based on circuit redesign and code replacement techniques. Simulation results show that the proposed methods improve performance and energy efficiency of an Arithmetic Logic Unit by 19% and 43%, respectively. Furthermore, the improved performance of the optimized circuits can be traded to improving the reliability.

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ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

Journal of Circuits System and Computers ◽

10.1142/s0218126613500485 ◽

2013 ◽

Vol 22 (06) ◽

pp. 1350048 ◽

Cited By ~ 1

Author(s):

SARAVANAN RAMAMOORTHY ◽

HAIBO WANG

Keyword(s):

Memory Effect ◽

Threshold Voltage ◽

Power Supply ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Technology ◽

Design Modification ◽

Offset Voltage ◽

Rail To Rail ◽

Near Threshold

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

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Body-Effect-Free OLED-on-Silicon Pixel Circuit Based on Capacitive Division to Extend Data Voltage Range

Electronics ◽

10.3390/electronics10192351 ◽

2021 ◽

Vol 10 (19) ◽

pp. 2351

Author(s):

Jina Bae ◽

Hyoungsik Nam

Keyword(s):

Threshold Voltage ◽

Supply Voltage ◽

The Body ◽

Body Effect ◽

Voltage Range ◽

Error Range ◽

Large Current ◽

Voltage Variation ◽

Current Error ◽

Node Voltage

This paper proposes an OLED pixel compensation circuit that copes with threshold voltage variation, narrow data voltage range, and body effect on a backplane of silicon-based transistors. It consists of six PMOS transistors and two capacitors. The data voltage range is extended by the capacitor division with two capacitors, and the connection of both source and gate nodes to the supply voltage makes the driving transistor free from the body effect. In addition, the reference voltage is used to initialize the gate node voltage of the driving transistor as well as to adjust the data voltage region. By the SPICE simulation, it is verified that the current error over the threshold voltage variations of ±10 mV is reduced to be −1.200% to 0.964% at the maximum current range of around 8 nA, and the data voltage range is extended to 3.4 V, compared to the large current error range from −21.46% to 27.36% and the data voltage range of 0.41 V in the basic 2T1C circuit. In addition, the body-effect-free circuit outperforms the latest 4T1C circuit of the current error range from −3.279% to 3.388%.

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