A 3.2ppm/°C curvature-compensated bandgap reference with wide supply voltage range

2012 ◽  
Vol 43 (11) ◽  
pp. 863-868 ◽  
Author(s):  
Ze-Kun Zhou ◽  
Xue-Chun Ou ◽  
Yue Shi ◽  
Pei-Sheng Zhu ◽  
Ying-Qian Ma ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Bandgap Reference ◽  
Voltage Range

scholarly journals A High-Accuracy Ultra-Low-Power Offset-Cancelation On-Off Bandgap Reference for Implantable Medical Electronics

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 814 ◽  
Author(s):  
Jiangtao Xu ◽  
Yawei Wang ◽  
Minshun Wu ◽  
Ruizhi Zhang ◽  
Sufen Wei ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Sampling Strategy ◽  
High Accuracy ◽  
Cmos Process ◽  
Medical Electronics ◽  
Bandgap Reference ◽  
Ultra Low Power ◽  
Voltage Range ◽  
Average Current

An ultra-low-power and high-accuracy on-off bandgap reference (BGR) is demonstrated in this paper for implantable medical electronics. The proposed BGR shows an average current consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy of 0.69%. The on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism allows a relatively higher current in the sample phase to alleviate the process variation of bipolar transistors. To compensate the error caused by operational amplifier offset, the correlated double sampling strategy is adopted in the BGR. The proposed BGR is implemented in 0.35 μm standard CMOS process and occupies a total area of 0.063 mm2. Measurement results show that the circuit works properly in the supply voltage range of 1.8–3.2 V and achieves a line regulation of 0.59 mV/V. When the temperature varies from −20 to 80 °C, an average temperature coefficient of 19.6 ppm/°C is achieved.

scholarly journals A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  
Keyword(s):  
Operational Amplifier ◽  
Supply Voltage ◽  
Bandgap Reference ◽  
Digital To Analog Converter ◽  
Future Design ◽  
Differential Nonlinearity ◽  
Self Bias ◽  
Analog Converter ◽  
Digital To Analog ◽  
Low Offset

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

scholarly journals T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Negative Charge ◽  
Switching Time ◽  
Supply Voltage ◽  
Charge Pump ◽  
Design Rule ◽  
Absolute Maximum ◽  
Optimum Number ◽  
Rf Switch ◽  
Voltage Range ◽  
Custom Made

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

A High Temperature 4H-SiC Voltage Reference for Depletion Mode GaN-Based Circuits

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000118-000121
Author(s):  
ZiHao Zhang ◽  
Jebreel M. Salem ◽  
Dong Sam Ha
Keyword(s):  
High Temperature ◽  
High Temperatures ◽  
Oil And Gas ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Voltage Range ◽  
Oil And Gas Exploration ◽  
Low Leakage ◽  
Temperature Applications

Abstract High temperature electronics are highly demanded for many applications such as automotive, space, and oil and gas exploration. Electronic circuits for those applications are required to operate reliably without using bulky cooling systems. Circuits based on silicon (Si) suffer from high leakage currents at high temperatures. Silicon Carbide (SiC) circuits, on the other hand, are suitable for high temperature applications due to the wide bandgap and offer high breakdown voltage and low leakage current. This paper presents a negative voltage reference for high temperature applications using commercial-off-the-shelf (COTS) 4H-SiC transistors. The proposed voltage reference adopts Widlar bandgap reference topology, and it aims to provide a negative reference voltage for Gallium Nitride (GaN) circuits operating at high temperatures. Measurement results indicate that the proposed circuit provides a negative reference voltage with a low temperature coefficient of 42 ppm/°C for temperatures ranging from 25 °C to 250 °C. The proposed circuit also operates reliably for a wide supply voltage range of −7.5 V to −15 V for the temperature range.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals A high supply voltage bandgap reference circuit using drain-extended MOS devices

2013 ◽  
Vol 10 (8) ◽  
pp. 20130142-20130142
Author(s):  
Geun Rae Cho ◽  
Kyung Woon Hwang ◽  
Tag Gon Kim
Keyword(s):  
Supply Voltage ◽  
Bandgap Reference ◽  
Mos Devices ◽  
Reference Circuit

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

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