scholarly journals Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency

Micromachines ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 590
Author(s):  
Wei-Kai Cheng ◽  
Po-Yuan Shen ◽  
Xin-Lun Li
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Integration Scheme ◽  
Data Loss ◽  
Access Memory ◽  
Cycle Times ◽  
Refresh Cycle ◽  
Dram Refresh ◽  
And Performance ◽  
The Given

Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in memory that have lower retention time, DRAM has to raise the refresh frequency to keep the data integrity, and hence produce unnecessary refreshes for the other normal cells, which results in a large refresh energy and performance delay of memory access. In this paper, we propose an integration scheme for DRAM refresh based on the retention-aware auto-refresh (RAAR) method and 2x granularity auto-refresh simultaneously. We also explain the corresponding modification need on memory controllers to support the proposed integration refresh scheme. With the given profile of weak cells distribution in memory banks, our integration scheme can choose the most appropriate refresh technique in each refresh time. Experimental results on different refresh cycle times show that the retention-aware refresh scheme can properly improve the system performance and have a great reduction in refresh energy. Especially when the number of weak cells increased due to the thermal effect of 3D-stacked architecture, our methodology still keeps the same performance and energy efficiency.

Set Programming Method and Performance Improvement of Phase Change Random Access Memory Arrays

2015 ◽  
Vol 32 (6) ◽  
pp. 068301 ◽  
Author(s):  
Xi Fan ◽  
Hou-Peng Chen ◽  
Qian Wang ◽  
Yue-Qing Wang ◽  
Shi-Long Lv ◽  
...  
Keyword(s):  
Phase Change ◽  
Performance Improvement ◽  
Random Access ◽  
Random Access Memory ◽  
Programming Method ◽  
Access Memory ◽  
Memory Arrays ◽  
And Performance

scholarly journals Análisis de las características Corriente-Voltaje (I-V) en Barreras Schottky de Silicio (p)-Oro

2019 ◽  
pp. 1-5
Author(s):  
Jonathan Ortiz-Vázquez ◽  
José Luis Ortiz-Simón ◽  
Gerardo Vázquez-Méndez ◽  
Gustavo Emilio Gustavo Emilio
Keyword(s):  
Storage Capacity ◽  
Low Cost ◽  
Random Access ◽  
Random Access Memory ◽  
Schottky Barriers ◽  
Memory Storage ◽  
Magnetic Orientation ◽  
Access Memory ◽  
Current Voltage ◽  
And Performance

The bandwidth, low cost, great storage capacity and performance are characteristics of the random Access Memories (RAM).Some kinds of RAM include ferro-random access memory (FRAM) and magnetoresistive random access memory (MRAM), the latter being of great interest to the scientific community since storage is achieved via magnetic orientation rather than electric orientation. In this paper, we analyze the effect of the application of an external magnetic field on the current-voltage (I-V) characteristics of Schottky barriers made of silicon-gold, to show the effects of magnetoresistance in dispositive semiconductors suited for use as memory storage.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature
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