Synthesis of Vertical Carbon Nanotube Interconnect Structures Using CMOS-Compatible Catalysts

Synthesis of the vertically aligned carbon nanotubes (CNTs) using complementary metal-oxide-semiconductor (CMOS)-compatible methods is essential to integrate the CNT contact and interconnect to nanoscale devices and ultra-dense integrated nanoelectronics. However, the synthesis of high-density CNT array at low-temperature remains a challenging task. The advances in the low-temperature synthesis of high-density vertical CNT structures using CMOS-compatible methods are reviewed. Primarily, recent works on theoretical simulations and experimental characterizations of CNT growth emphasized the critical roles of catalyst design in reducing synthesis temperature and increasing CNT density. In particular, the approach of using multilayer catalyst film to generate the alloyed catalyst nanoparticle was found competent to improve the active catalyst nanoparticle formation and reduce the CNT growth temperature. With the multilayer catalyst, CNT arrays were directly grown on metals, oxides, and 2D materials. Moreover, the relations among the catalyst film thickness, CNT diameter, and wall number were surveyed, which provided potential strategies to control the tube density and the wall density of synthesized CNT array.

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Low Temperature Synthesis of High-Density Carbon Nanotubes on Insulating Substrate

Nanomaterials ◽

10.3390/nano9030473 ◽

2019 ◽

Vol 9 (3) ◽

pp. 473 ◽

Cited By ~ 3

Author(s):

Ying Xiao ◽

Zubair Ahmed ◽

Zichao Ma ◽

Changjian Zhou ◽

Lining Zhang ◽

...

Keyword(s):

Carbon Nanotubes ◽

Low Temperature ◽

High Surface ◽

Chemical Vapor ◽

Synthesis Temperature ◽

Catalyst Design ◽

High Density ◽

Oxide Semiconductor ◽

Multi Wall Carbon Nanotubes ◽

Vertically Aligned

A method to synthesize high-density, vertically-aligned, multi-wall carbon nanotubes (MWCNTs) on an insulating substrate at low temperature using a complementary metal–oxide–semiconductor (CMOS) compatible process is presented. Two factors are identified to be important in the carbon nanotube (CNT) growth, which are the catalyst design and the substrate material. By using a Ni–Al–Ni multilayer catalyst film and a ZrO2 substrate, vertically-aligned CNTs can be synthesized at 340 °C using plasma-enhanced chemical vapor deposition (PECVD). Both the quality and density of the CNTs can be enhanced by increasing the synthesis temperature. The function of the aluminum interlayer in reducing the activation energy of the CNT formation is studied. The nanoparticle sintering and quick accumulation of amorphous carbon covering the catalyst can prematurely stop CNT synthesis. Both effects can be suppressed by using a substrate with a high surface energy such as ZrO2.

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Development of a CMOS-Compatible Carbon Nanotube Array Transfer Method

Micromachines ◽

10.3390/mi12010095 ◽

2021 ◽

Vol 12 (1) ◽

pp. 95

Author(s):

Chun Fei Siah ◽

Lucas Yu Xiang Lum ◽

Jianxiong Wang ◽

Simon Chun Kiat Goh ◽

Chong Wei Tan ◽

...

Keyword(s):

High Growth ◽

Complementary Metal Oxide Semiconductor ◽

Thermal Interface Material ◽

Oxide Semiconductor ◽

Interfacial Resistance ◽

Alignment Tool ◽

Starting Point ◽

Cnt Arrays ◽

Cmos Compatible ◽

Transfer Method

Carbon nanotubes (CNTs) have, over the years, been used in research as a promising material in electronics as a thermal interface material and as interconnects amongst other applications. However, there exist several issues preventing the widespread integration of CNTs onto device applications, e.g., high growth temperature and interfacial resistance. To overcome these issues, a complementary metal oxide semiconductor (CMOS)-compatible CNT array transfer method that electrically connects the CNT arrays to target device substrates was developed. The method separates the CNT growth and preparation steps from the target substrate. Utilizing an alignment tool with the capabilities of thermocompression enables a highly accurate transfer of CNT arrays onto designated areas with desired patterns. With this transfer process as a starting point, improvement pointers are also discussed in this paper to further improve the quality of the transferred CNTs.

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Applicability of independent component analysis on high-density microelectrode array recordings

Journal of Neurophysiology ◽

10.1152/jn.01106.2011 ◽

2012 ◽

Vol 108 (1) ◽

pp. 334-348 ◽

Cited By ~ 41

Author(s):

David Jäckel ◽

Urs Frey ◽

Michele Fiscella ◽

Felix Franke ◽

Andreas Hierlemann

Keyword(s):

Microelectrode Array ◽

Simulated Data ◽

Complementary Metal Oxide Semiconductor ◽

Simultaneous Recording ◽

High Density ◽

Independent Component ◽

Oxide Semiconductor ◽

Spike Sorting ◽

Spatiotemporal Resolution ◽

Source Signals

Emerging complementary metal oxide semiconductor (CMOS)-based, high-density microelectrode array (HD-MEA) devices provide high spatial resolution at subcellular level and a large number of readout channels. These devices allow for simultaneous recording of extracellular activity of a large number of neurons with every neuron being detected by multiple electrodes. To analyze the recorded signals, spiking events have to be assigned to individual neurons, a process referred to as “spike sorting.” For a set of observed signals, which constitute a linear mixture of a set of source signals, independent component (IC) analysis (ICA) can be used to demix blindly the data and extract the individual source signals. This technique offers great potential to alleviate the problem of spike sorting in HD-MEA recordings, as it represents an unsupervised method to separate the neuronal sources. The separated sources or ICs then constitute estimates of single-neuron signals, and threshold detection on the ICs yields the sorted spike times. However, it is unknown to what extent extracellular neuronal recordings meet the requirements of ICA. In this paper, we evaluate the applicability of ICA to spike sorting of HD-MEA recordings. The analysis of extracellular neuronal signals, recorded at high spatiotemporal resolution, reveals that the recorded data cannot be modeled as a purely linear mixture. As a consequence, ICA fails to separate completely the neuronal signals and cannot be used as a stand-alone method for spike sorting in HD-MEA recordings. We assessed the demixing performance of ICA using simulated data sets and found that the performance strongly depends on neuronal density and spike amplitude. Furthermore, we show how postprocessing techniques can be used to overcome the most severe limitations of ICA. In combination with these postprocessing techniques, ICA represents a viable method to facilitate rapid spike sorting of multidimensional neuronal recordings.

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Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

Japanese Journal of Applied Physics ◽

10.1143/jjap.45.3202 ◽

2006 ◽

Vol 45 (4B) ◽

pp. 3202-3206 ◽

Cited By ~ 10

Author(s):

K. R. Udayakumar ◽

K. Boku ◽

K. A. Remack ◽

J. Rodriguez ◽

S. R. Summerfelt ◽

...

Keyword(s):

Metal Oxide ◽

Random Access ◽

Complementary Metal Oxide Semiconductor ◽

Random Access Memory ◽

Metal Oxide Semiconductor ◽

High Density ◽

Oxide Semiconductor ◽

Access Memory ◽

Ferroelectric Random Access Memory

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Low-temperature formation of highly reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal–oxide–semiconductor technology

Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena ◽

10.1116/1.1491550 ◽

2002 ◽

Vol 20 (4) ◽

pp. 1406 ◽

Cited By ~ 7

Author(s):

Anri Nakajima ◽

Quazi Deen Mohd Khosru ◽

Takashi Yoshimoto ◽

Toshirou Kidera ◽

Shin Yokoyama

Keyword(s):

Silicon Nitride ◽

Low Temperature ◽

Metal Oxide ◽

Gate Dielectrics ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Semiconductor Technology ◽

Soft Breakdown

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Open Circuit Voltage and Single Walled Carbon Nanotube (wt%) Dependency in Solid-State Complementary Metal Oxide Semiconductor-Compatible Glucose Fuel Cells

Nanoscience and Nanotechnology Letters ◽

10.1166/nnl.2020.3085 ◽

2020 ◽

Vol 12 (1) ◽

pp. 101-106

Author(s):

Md. Zahidul Islam ◽

Shigeki Arata ◽

Kenya Hayashi ◽

Atsuki Kobayashi ◽

Kiichi Niitsu

Keyword(s):

Carbon Nanotube ◽

Fuel Cell ◽

Open Circuit Voltage ◽

Complementary Metal Oxide Semiconductor ◽

Open Circuit ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Single Walled Carbon Nanotube ◽

Single Walled Carbon ◽

Cmos Compatible

Solid-state complementary metal oxide semiconductor (CMOS)-compatible glucose fuel cells, with single-walled carbon nanotube (SWCNT) films and different amounts of carbon nanotube (wt%) were investigated. Those with a SWCNT content of 3 wt% were found to develop the highest open circuit voltage (OCV) of 400 mV, together with a high electrical conductivity, a power density of 0.53 μW/cm2 and current density of 1.31 μA/cm2. Measurements were performed by dipping the anode into a 30 mM glucose solution. The OCV and power density increased together with the fuel cell concentration. The developed fuel cell uses materials that are biocompatible with the human body (single-walled carbon nanotube-glucose). As a result, it was possible to attain an OCV of 400 mV with a single-walled carbon nanotube content of 3 wt% while improvements in the performance of the CMOS-compatible glucose fuel cell were obtained, and the parameters affecting the performance of the fuel cell were identified. This bio-fuel cell was fabricated using CMOS semiconductor processes on a silicon wafer. These findings are significant to realizing mobile or implantable devices that can be used for biomedical applications.

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A CMOS Compatible Metal-Polymer Microchannel Heat Sink for Monolithic Chip Cooling Applications

2010 14th International Heat Transfer Conference, Volume 3 ◽

10.1115/ihtc14-23212 ◽

2010 ◽

Cited By ~ 1

Author(s):

Aziz Koyuncuog˘lu ◽

Tuba Okutucu ◽

Haluk Ku¨lah

Keyword(s):

Heat Sink ◽

Complementary Metal Oxide Semiconductor ◽

Heat Sinks ◽

Oxide Semiconductor ◽

Microchannel Heat Sink ◽

Liquid Cooling ◽

Chip Cooling ◽

Electronic Circuitry ◽

Cmos Compatible ◽

Adjacent Channels

A novel complementary metal oxide semiconductor (CMOS) compatible microchannel heat sink is designed and fabricated for monolithic liquid cooling of electronic circuits. The microchannels are fabricated with full metal walls between adjacent channels with a polymer top layer for easy sealing and optical visibility of the channels. The use of polymer also provides flexibility in adjusting the width of the channels allowing better management of the pressure drop. The proposed microchannel heat sink requires no design change of the electronic circuitry underneath, hence, can be produced by adding a few more steps to the standard CMOS fabrication flow. The microchannel heat sinks were tested successfully under various heat flux and coolant flow rate conditions. The preliminary cooling tests indicate that the proposed design is promising as a monolithic liquid cooling solution for CMOS circuits.

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CMOS-compatible photonic devices for single-photon generation

Nanophotonics ◽

10.1515/nanoph-2016-0022 ◽

2016 ◽

Vol 5 (3) ◽

pp. 427-439 ◽

Cited By ~ 14

Author(s):

Chunle Xiong ◽

Bryn Bell ◽

Benjamin J. Eggleton

Keyword(s):

Secure Communication ◽

Single Photon ◽

Complementary Metal Oxide Semiconductor ◽

Building Blocks ◽

Photonic Devices ◽

Oxide Semiconductor ◽

Single Photons ◽

Quantum Secure Communication ◽

Cmos Compatible ◽

Photon Generation

AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

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