scholarly journals A Near-Zero Power Triboelectric Wake-Up System for Autonomous Beaufort Scale of Wind Force Monitoring

2021 ◽  
Vol 1 (2) ◽  
pp. 121-130
Author(s):  
Tong Tong ◽  
Guoxu Liu ◽  
Yuan Lin ◽  
Shaohang Xu ◽  
Chi Zhang
Keyword(s):  
Power Consumption ◽  
Electric Energy ◽  
Battery Life ◽  
Wind Force ◽  
Active Mode ◽  
Static Power ◽  
Force Monitoring ◽  
Important Means ◽  
System Life ◽  
Timely Warning

Beaufort scale of wind force monitoring is the basic content of meteorological monitoring, which is an important means to ensure the safety of production and life by timely warning of natural disasters. As there is a limited battery life for sensors, determining how to reduce power consumption and extend system life is still an urgent problem. In this work, a near-zero power triboelectric wake-up system for autonomous Beaufort scale of wind force monitoring is proposed, in which a rotary TENG is used to convert wind energy into a stored electric energy capacitor. When the capacitor voltage accumulates to the threshold voltage of a transistor, it turns on as an electronic switch and the system wakes up. In active mode, the Beaufort scale of wind force can be judged according to the electric energy and the signal is sent out wirelessly. In standby mode, when there is no wind, the power consumption of the system is only 14 nW. When the wind scale reaches or exceeds light air, the system can switch to active mode within one second and accurately judge the Beaufort scale of wind force within 10 s. This work provided a triboelectric sensor-based wake-up system with ultralow static power consumption, which has great prospects for unattended environmental monitoring, hurricane warning, and big data acquisition.

scholarly journals Dynamic Power Optimization of 32 Bit MIPS Processor Using Clock Gating For Low Power Applications

2019 ◽  
Vol 8 (2) ◽  
pp. 5936-5941
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Design ◽  
Total Power ◽  
Battery Life ◽  
Clock Gating ◽  
Dynamic Power ◽  
Total Power Consumption ◽  
Static Power ◽  
Major Factors

The demand for low power processor is increasing day by day in mobile application for video, audio, mixed signal processing, gaming console and battery-operated electronic devices. Power consumption is the main issue in batter operated devices which constantly reduces battery life. Compared to static power Dynamic power yields more power consumption in digital design. Clock power is one of the major factors in total power consumption which results in high dynamic power consumption. In this paper, a 32-bit MIPS processor is designed to maximize the performance while considering the battery life of the device. Clock gating and data gating method is adopted in this paper and to reduce dynamic power. This design is implemented on 28nm kintex-7 FPGA Board and power is analyzed

Design for Test and Diagnosis of Power Switches

2015 ◽  
Vol 25 (03) ◽  
pp. 1640013
Author(s):  
Miroslav Valka ◽  
Alberto Bosio ◽  
Luigi Dilillo ◽  
Patrick Girard ◽  
Arnaud Virazel ◽  
...  
Keyword(s):  
Power Consumption ◽  
Industrial Test ◽  
Design For Test ◽  
Power Gating ◽  
Test Quality ◽  
Worst Case ◽  
Manufacturing Defects ◽  
Efficient Test ◽  
Power Switches ◽  
Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals Class-C Linearized Amplifier for Portable Ultrasound Instruments

Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 898 ◽  
Author(s):  
Hojong Choi
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
Signal Amplitude ◽  
Piezoelectric Transducers ◽  
Battery Life ◽  
Potential Candidate ◽  
Portable Ultrasound ◽  
Dc Power ◽  
Class C ◽  
Main Components

Transistor linearizer networks are proposed to increase the transmitted output voltage amplitudes of class-C amplifiers, thus, increasing the sensitivity of the echo signals of piezoelectric transducers, which are the main components in portable ultrasound instruments. For such instruments, class-C amplifiers could be among the most efficient amplifier schemes because, compared with a linear amplifier such as a class-A amplifier, they could critically reduce direct current (DC) power consumption, thus, increasing the battery life of the instruments. However, the reduced output voltage amplitudes of class-C amplifiers could deteriorate the sensitivity of the echo signals, thereby affecting the instrument performance. Therefore, a class-C linearized amplifier was developed. To verify the capability of the class-C linearized amplifier, typical pulse-echo responses using the focused piezoelectric transducers were tested. The echo signal amplitude generated by the piezoelectric transducers when using the class-C linearized amplifier was improved (1.29 Vp-p) compared with that when using the class-C amplifier alone (0.56 Vp-p). Therefore, the class-C linearized amplifier could be a potential candidate to increase the sensitivity of echo signals while reducing the DC power consumption for portable ultrasound instruments.

Various Issues and considerations for the Static Power Consumption in NANO-CMOS: Design Perspective

2019 ◽  
Vol 10 ◽  
pp. 136-141 ◽  
Author(s):  
Ashwani Kumar Yadav ◽  
Kartik Upadhyay ◽  
Palak Gandhi ◽  
Vaishali
Keyword(s):  
Power Consumption ◽  
Cmos Design ◽  
Static Power ◽  
Design Perspective

Thermoelectric Generators Embedded in Microelectronic Chip

2012 ◽  
Author(s):  
Owen Sullivan ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Power Generation ◽  
Heat Flux ◽  
Power Consumption ◽  
Conversion Efficiency ◽  
Waste Heat ◽  
Average Power ◽  
Total Power ◽  
Battery Life ◽  
Thermoelectric Generators ◽  
Useful Power

Thermoelectric generators (TEGs) can significantly improve the net power consumption and battery life of the mobile devices or high performance devices by generating power from the waste heat of these devices. Recent advancements show that the ultrathin thermoelectric devices can be fabricated and integrated within a microelectronic package. This paper first investigates the power generation by a single ultrathin TEG embedded within a micro-electronic package considering several key factors such as load resistance, chip heat flux, and proximity of the TEG to chip. We observe that the power generation from TEGs increases with increasing background heat flux on chip or when TEGs are moved closer to the chip. After the investigation of a single TEG, an array of embedded TEGs is considered in order to analyze the influence of multiple TEGs on total power generation and conversion efficiency. Increasing the number of TEGs from one to nine increase the useful power generation from 72.9 mW to 378.4 mW but decreases the average conversion efficiency from 0.47% to 0.32%. This suggests that average power generated per TEG gradually decrease from 72.9 mW to 42.0 mW when number of TEGs is increased from one to nine. However, the total useful power generated using nine TEGs is significant and emphasize the benefits of using embedded TEGs to reduce net power consumption in electronics packages.

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

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