scholarly journals High Efficiency RF Energy Harvesting CNTFET Rectifier for Bio-implants Applications

2019 ◽  
Vol 9 (1) ◽  
pp. 4396-4402
Keyword(s):  
Field Effect Transistor ◽  
High Efficiency ◽  
Complementary Metal Oxide Semiconductor ◽  
Implantable Devices ◽  
Oxide Semiconductor ◽  
Full Wave ◽  
Type Device ◽  
Effect Transistor ◽  
Stanford Model ◽  
P Type

Carbon nanotube field effect transistor (CNTFET) based full wave rectifier given in the paper, works efficiently in the range of radio frequency. The CNTFET offers extremely less power loss and high through-put because of its high conducting properties. The Complementary Metal Oxide Semiconductor (CMOS) based studies are available but CNTFET based studies are rarely available. Therefore, CNTFET based rectifier has been used for the replacement of CMOS based rectifier architecture. The full wave rectifier circuit was analyzed using 32nm CNTFET Stanford model. An additional circuit of clampers is also used for introducing a negative DC level. Introduced negative DC signal further negated RF input signal and combined signal used for biasing the p type device during its conduction cycle. The CNTFET based rectifier with clamper circuit decreases the effective threshold voltage of switching p CNTFETs. The circuit resulted better RF input sensitivity of the transistor. Results show that 77.7% power conversion efficiency is suitable for powering up the bio-implantable devices.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 851 ◽  
Author(s):  
Gil-Tomàs ◽  
Gracia-Morán ◽  
Saiz-Adalid ◽  
Gil-Vicente
Keyword(s):  
Field Effect Transistor ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Graphene Nanoribbon ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fault Models ◽  
New Materials ◽  
Effect Transistor

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

scholarly journals CMOS-Based Physically Unclonable Functions: A Review and Tutorial

2021 ◽  
Author(s):  
Kamal Y. Kamal ◽  
Radu Muresan ◽  
Arafat Al-Dweik
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Fabrication Process ◽  
Oxide Semiconductor ◽  
Physically Unclonable Functions ◽  
Effect Transistor

<p>This article reviews complementary metal-oxide-semiconductor (CMOS) based physically unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process. Random <a>variations</a> at transistor level lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a unique response. This article discusses various concepts which allow for more variations at CMOS technology, layout, masking, and design levels. It also discusses various PUF related topics.</p>

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