scholarly journals The Impact of Mobile DIS and Rank-Decreased Attacks in Internet of Things Networks

2020 ◽  
Vol 10 (2) ◽  
pp. 66-72
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Low Power ◽  
Critical Evaluation ◽  
Average Power ◽  
The Internet ◽  
Delivery Ratio ◽  
Packet Delivery ◽  
Average Power Consumption ◽  
The Impact

With a predicted 50 billion devices by the end of 2020, the Internet of things has grown exponentially in the last few years. This growth has seen an increasing demand for mobility support in low power and lossy sensor networks, a type of network characterized by several limitations in terms of their resources including CPU, memory and batter, causing manufactures to push products out to the market faster, without the necessary security features. IoT networks rely on the Routing Protocol for Low Power and Lossy Network (RPL) for communication, designed by the Internet Engineering Task Force (IETF). This protocol has been proven to be efficient in relation to the handling of routing in such constrained networks, However, research studies revealed that RPL was inherently designed for static networks, indicating poor handling of mobile or dynamic topologies which is worsen when introducing mobile attacker. In this paper, two IoT routing attacks are evaluated under a mobile attacker with the aim of providing a critical evaluation of the impact the attacks have on the network in comparison to the case with static attacker. The first attack is the Rank attack in which the attacker announces false routing information to its neighbour attracting them to forward their data via the attacker. The second attack is the DIS attack in which the attacker floods the network with DIS messages triggering them to reset their transmission timers and sending messages more frequently. The comparison were conducted in terms of average power consumption and also the packet delivery ratio (PDR). Based on the results collected from the simulations, it was established that when an attacking node is mobile, there’s an average increase of 36.6 in power consumption and a decrease of 14 for packet delivery ratios when compared to a static attacking node.

scholarly journals Incorporating IEEE 1609.2-2016 Standard with Internet of Things-Based Low Power WAVE Devices

2020 ◽  
Vol 55 (1) ◽  
Author(s):  
Yaarob Al-Nidawi ◽  
Mahmood Zaki Abdullah
Keyword(s):  
Internet Of Things ◽  
Low Power ◽  
Wireless Access ◽  
The Internet ◽  
Power Devices ◽  
Internet Of Vehicles ◽  
Power Wave ◽  
The Impact ◽  
The Internet Of Things ◽  
Access Security

The integration of low-power devices in different aspects of life has increased the challenges of mitigating the impact of the heterogeneity of different related technologies. Accordingly, the Internet of Things context is an umbrella that diffuses different proprietary protocols into standardized forms to overcome the heterogeneity problem. The recent IEEE 1609.2-2016 standard is tackling the issue of wireless access security in the vehicular environment. An obstacle arose by which Internet of Things-based, low-power devices are integrated into the Internet of Vehicles cloud. In turn, the overhead of Internet of Vehicles-based protocols must be analyzed regarding the adaptability of low-power devices in the vehicular environment. This paper investigates the burden of the IEEE 1609.2 security stack on Internet of Things-based, limited-capability devices and defines the possible approaches to incorporate these low-power devices within the vehicular network under the IEEE 1609.2 standard. The proposed methodology, through the conducted simulations, demonstrates low security overhead with a 40% reduction in consumed energy over the default WAVE stack. In addition, the results show that including low-power devices within the Internet of Vehicles paradigm is possible, but still more enhancements and contributions are required to minimize the overhead of the WAVE security stack.

scholarly journals A configurable fluorescence sensing front-end for ultra-low power and high sensitivity applications

2021 ◽  
Author(s):  
Maryam Rafati ◽  
Seyed Ruhallah Qasemi ◽  
Atila Alvandpour
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Excitation Frequency ◽  
Average Power ◽  
High Sensitivity ◽  
Current Noise ◽  
Fluorescence Sensing ◽  
Ultra Low Power ◽  
Front End ◽  
Average Power Consumption

AbstractThis paper presents an ultra-low power, high sensitivity configurable CMOS fluorescence sensing front-end for implantable biosensors at single-cell level measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, an ambient light canceling technique is proposed to make the sensor operate under different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is designed and fabricated in a 0.35 µm standard CMOS technology, and the measurement results are presented. The minimum integrated input-referred current noise is measured as 1.07 pA with the total average power consumption of 61.8 µW at an excitation frequency of 80 Hz. For ultra-low-power configuration, the front-end has an average power consumption of 119 nW and input integrated current noise of 210 pA at an excitation frequency of 20 kHz.

scholarly journals RPL LOAD BALANCING IN INTERNET OF THINGS

2017 ◽  
Vol 18 (2) ◽  
pp. 137-150 ◽  
Author(s):  
Mohammad Reza Parsaei ◽  
Ahmad Reza Parnian ◽  
Samaneh Miri Rostami ◽  
Reza Javidan
Keyword(s):  
Internet Of Things ◽  
Load Balancing ◽  
Low Power ◽  
Packet Delivery Ratio ◽  
Delivery Ratio ◽  
Lossy Networks ◽  
Smart Objects ◽  
Packet Delivery ◽  
End To End Delay ◽  
End To End

ABSTRACT:  The wide address space provided by Internet Protocol version 6 (IPv6) lets any thing to be identified uniquely. consistency of the modified version of IPv6 protocol stack with smart objects, facilitated the Internet interconnection of the networks of smart objects and introduced Internet of things. A smart object is a small micro-electronic device that consists of a communication device, a small microprocessor and a sensor or an actuator. A network made of such devices is called low-power and lossy network. RPL routing protocol that is consistent to IPv6, is designed to be used in these kinds of networks. Load balancing is not considered in the RPL design process. Whenever RPL is used in large scale low-power and lossy networks some nodes will suffer from congestion and this problem severely degrades network performance. In this paper, we consider solutions provided to tackle RPL load balancing problems. Load balancing algorithms and protoclos are evaluated through simulation. We evaluate IETF RPL implementation and LB-RPL method with Contiki OS Java (COOJA) simulator. They are assessed comprehensively through metrics such as Packet delivery Ratio, Average End to End delay, and Gateway Throughput. LB-RPL improves RPL in terms of Packet delivery Ratio and throughput but increases Average End to End delay. Simulations results show that RPL load balancing needs extensive works to be performed yet.

scholarly journals History-based consistency algorithm for the trickle-timer with low-power and lossy networks

2021 ◽  
Vol 11 (3) ◽  
pp. 2569
Author(s):  
Firas A. Albalas ◽  
Haneen Taamneh ◽  
Wail E. Mardini
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Routing Protocol ◽  
Convergence Time ◽  
Limited Resources ◽  
The Internet ◽  
Delivery Ratio ◽  
Lossy Networks ◽  
Main Components ◽  
The Internet Of Things

Recently, the internet of things (IoT) has become an important concept which has changed the vision of the Internet with the appearance of IPv6 over low power and lossy networks (6LoWPAN). However, these 6LoWPANs have many drawbacks because of the use of many devices with limited resources; therefore, suitable protocols such as the Routing Protocol for low power and lossy networks (RPL) were developed, and one of RPL's main components is the trickle timer algorithm, used to control and maintain the routing traffic frequency caused by a set of control messages. However, the trickle timer suffered from the short-listen problem which was handled by adding the listen-only period mechanism. This addition increased the delay in propagating transmissions and resolving the inconsistency in the network. However, to solve this problem we proposed the history based consistency algorithm (HBC), which eliminates the listen-only period based on the consistency period of the network. The proposed algorithm showed very good results. We measured the performance of HBC trickle in terms of convergence time; which was mainly affected, the power consumption and the packet delivery ratio (PDR). We made a comparison between the original trickle timer, the E-Trickle, the optimized trickle and our HBC trickle algorithm. The PDR and the power consumption showed in some cases better results under the HBC trickle compared to other trickle timers and in other cases the results were very close to the original trickle indicating the efficiency of the proposed trickle in choosing optimal routes when sending messages.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

scholarly journals 3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1217
Author(s):  
Yu Gan ◽  
Hong Guo ◽  
Ziheng Zhou
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Low Power ◽  
Simulated Annealing Algorithm ◽  
Average Power ◽  
Global Optimum ◽  
Initial Population ◽  
Improved Genetic Algorithm ◽  
Average Power Consumption ◽  
Ip Cores

Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP (Intellectual Property) cores to 3D NoC. First, in view of the randomness of the traditional genetic algorithm in individual selection, an improved greedy algorithm is used in the initial population generation stage to make the generated individuals reach the optimal. Secondly, in view of the weak local optimization ability of the traditional genetic algorithm and prone to premature problems, the simulated annealing algorithm is added in the crossover operation stage to make the offspring reach the global optimum. The experimental results show that compared with the traditional genetic algorithm, the algorithm has better convergence and low power consumption performance, which can quickly search for a better solution, in the case of a large number of cores (124 IP cores), the average power consumption can be reduced by 42.2%.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

2015 ◽  
Vol 24 (09) ◽  
pp. 1550134 ◽  
Author(s):  
Seied Zaniar Hoseini ◽  
Johar Abdekhoda ◽  
Kye-Shin Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Average Power ◽  
Threshold Region ◽  
Clock Frequency ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sensing Applications ◽  
Average Power Consumption

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

scholarly journals A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

2022 ◽  
Vol 8 (1) ◽  
Author(s):  
Stefan Nedelcu ◽  
Kishan Thodkar ◽  
Christofer Hierold
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Limit Of Detection ◽  
Sampling Rate ◽  
Average Power ◽  
Physical Parameters ◽  
Embedded Sensing ◽  
Sensing Applications ◽  
Measurement Protocol ◽  
Average Power Consumption

AbstractCustomizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

scholarly journals Influence of low power consumption on IEEE 802.15.4 in wireless networks performance

2020 ◽  
Vol 9 (1) ◽  
pp. 205-211
Author(s):  
A. Z. Yonis
Keyword(s):  
Phase Shift ◽  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Cost ◽  
Average Power ◽  
Low Power Consumption ◽  
Media Access Control ◽  
Battery Life ◽  
Average Power Consumption

IEEE 802.15.4 standard defines both media access control (MAC) and physical (PHY) layer protocols for low power consumption, low peak data rate, and low cost applications. Nowadays the most important feature of IEEE 802.15.4 is maximizing battery life. This paper is focusing how to achieve low average power consumption through assuming that the amount of data transmitted is short and that it is transmitted infrequently so as to keep a low duty cycle. The outcomes demonstrate that the phase shift estimation of Offset quadrature phase-shift keying (OQPSK) modulation has no impact on bit error rate (BER) if it is identical in the transmitter as same as in the receiver.

Sign in / Sign up

Export Citation Format

Share Document