scholarly journals A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

2022 ◽  
Vol 8 (1) ◽  
Author(s):  
Stefan Nedelcu ◽  
Kishan Thodkar ◽  
Christofer Hierold
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Limit Of Detection ◽  
Sampling Rate ◽  
Average Power ◽  
Physical Parameters ◽  
Embedded Sensing ◽  
Sensing Applications ◽  
Measurement Protocol ◽  
Average Power Consumption

AbstractCustomizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

2015 ◽  
Vol 24 (09) ◽  
pp. 1550134 ◽  
Author(s):  
Seied Zaniar Hoseini ◽  
Johar Abdekhoda ◽  
Kye-Shin Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Average Power ◽  
Threshold Region ◽  
Clock Frequency ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sensing Applications ◽  
Average Power Consumption

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

scholarly journals A configurable fluorescence sensing front-end for ultra-low power and high sensitivity applications

2021 ◽  
Author(s):  
Maryam Rafati ◽  
Seyed Ruhallah Qasemi ◽  
Atila Alvandpour
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Excitation Frequency ◽  
Average Power ◽  
High Sensitivity ◽  
Current Noise ◽  
Fluorescence Sensing ◽  
Ultra Low Power ◽  
Front End ◽  
Average Power Consumption

AbstractThis paper presents an ultra-low power, high sensitivity configurable CMOS fluorescence sensing front-end for implantable biosensors at single-cell level measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, an ambient light canceling technique is proposed to make the sensor operate under different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is designed and fabricated in a 0.35 µm standard CMOS technology, and the measurement results are presented. The minimum integrated input-referred current noise is measured as 1.07 pA with the total average power consumption of 61.8 µW at an excitation frequency of 80 Hz. For ultra-low-power configuration, the front-end has an average power consumption of 119 nW and input integrated current noise of 210 pA at an excitation frequency of 20 kHz.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

scholarly journals 3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1217
Author(s):  
Yu Gan ◽  
Hong Guo ◽  
Ziheng Zhou
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Low Power ◽  
Simulated Annealing Algorithm ◽  
Average Power ◽  
Global Optimum ◽  
Initial Population ◽  
Improved Genetic Algorithm ◽  
Average Power Consumption ◽  
Ip Cores

Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP (Intellectual Property) cores to 3D NoC. First, in view of the randomness of the traditional genetic algorithm in individual selection, an improved greedy algorithm is used in the initial population generation stage to make the generated individuals reach the optimal. Secondly, in view of the weak local optimization ability of the traditional genetic algorithm and prone to premature problems, the simulated annealing algorithm is added in the crossover operation stage to make the offspring reach the global optimum. The experimental results show that compared with the traditional genetic algorithm, the algorithm has better convergence and low power consumption performance, which can quickly search for a better solution, in the case of a large number of cores (124 IP cores), the average power consumption can be reduced by 42.2%.

scholarly journals Influence of low power consumption on IEEE 802.15.4 in wireless networks performance

2020 ◽  
Vol 9 (1) ◽  
pp. 205-211
Author(s):  
A. Z. Yonis
Keyword(s):  
Phase Shift ◽  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Cost ◽  
Average Power ◽  
Low Power Consumption ◽  
Media Access Control ◽  
Battery Life ◽  
Average Power Consumption

IEEE 802.15.4 standard defines both media access control (MAC) and physical (PHY) layer protocols for low power consumption, low peak data rate, and low cost applications. Nowadays the most important feature of IEEE 802.15.4 is maximizing battery life. This paper is focusing how to achieve low average power consumption through assuming that the amount of data transmitted is short and that it is transmitted infrequently so as to keep a low duty cycle. The outcomes demonstrate that the phase shift estimation of Offset quadrature phase-shift keying (OQPSK) modulation has no impact on bit error rate (BER) if it is identical in the transmitter as same as in the receiver.

scholarly journals Design of a Low-Power Radio Frequency Unit and Its Application for Bacterial Inactivation under Laboratory Conditions

2021 ◽  
Vol 11 (23) ◽  
pp. 11117
Author(s):  
Dmytro S. Kozak ◽  
Maria Tonti ◽  
Patricia Cuba ◽  
Julian Espitia ◽  
Vladimir S. Tsepelev ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Radio Frequency ◽  
Average Power ◽  
Brain Heart Infusion ◽  
Added Value ◽  
Growth Media ◽  
Bacterial Inactivation ◽  
Operational Parameters ◽  
Average Power Consumption

A lab-scale low-power free-running radio frequency (RF) oscillator operating at a frequency of 27.12 ± 0.50 MHz was developed to be suitable for fundamental microbiological research topics. Calibration and validation were conducted for two common foodborne pathogens in relevant microbiological growth media, i.e., Salmonella Typhimurium and Listeria monocytogenes in Tryptic Soy Broth and Brain–Heart Infusion broth, respectively. The evolution of temperature, frequency, and power consumption was monitored during treatments, both with and without bacterial cells. The setup operated within the predefined frequency range, reaching temperatures of 71–76 °C after 15 min. The average power consumption ranged between 12 and 14 W. The presence of bacteria did not significantly influence the operational parameters. The inactivation potential of the RF setup was validated, demonstrating the absence of viable cells after 8 and 10 min of treatment, for S. Typhimurium and L. monocytogenes, respectively. In future studies, the setup can be used to conduct fundamental microbiological studies on RF inactivation. The setup can provide added value to the scientific field, since (i) no consensus has been reached on the inactivation mechanisms of RF inactivation of pathogens in foods and (ii) most commercial RF setups are unsuitable to adopt for fundamental studies.

scholarly journals The Impact of Mobile DIS and Rank-Decreased Attacks in Internet of Things Networks

2020 ◽  
Vol 10 (2) ◽  
pp. 66-72
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Low Power ◽  
Critical Evaluation ◽  
Average Power ◽  
The Internet ◽  
Delivery Ratio ◽  
Packet Delivery ◽  
Average Power Consumption ◽  
The Impact

With a predicted 50 billion devices by the end of 2020, the Internet of things has grown exponentially in the last few years. This growth has seen an increasing demand for mobility support in low power and lossy sensor networks, a type of network characterized by several limitations in terms of their resources including CPU, memory and batter, causing manufactures to push products out to the market faster, without the necessary security features. IoT networks rely on the Routing Protocol for Low Power and Lossy Network (RPL) for communication, designed by the Internet Engineering Task Force (IETF). This protocol has been proven to be efficient in relation to the handling of routing in such constrained networks, However, research studies revealed that RPL was inherently designed for static networks, indicating poor handling of mobile or dynamic topologies which is worsen when introducing mobile attacker. In this paper, two IoT routing attacks are evaluated under a mobile attacker with the aim of providing a critical evaluation of the impact the attacks have on the network in comparison to the case with static attacker. The first attack is the Rank attack in which the attacker announces false routing information to its neighbour attracting them to forward their data via the attacker. The second attack is the DIS attack in which the attacker floods the network with DIS messages triggering them to reset their transmission timers and sending messages more frequently. The comparison were conducted in terms of average power consumption and also the packet delivery ratio (PDR). Based on the results collected from the simulations, it was established that when an attacking node is mobile, there’s an average increase of 36.6 in power consumption and a decrease of 14 for packet delivery ratios when compared to a static attacking node.

Power Saving Schemes for Extending the Lifetime of IoT Smart City Applications

2020 ◽  
pp. 68-93
Author(s):  
Christopher Teh Jun Qian ◽  
Micheal Drieberg ◽  
Patrick Sebastian ◽  
Azrina Abd Aziz ◽  
Hai Hiung Lo ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Smart City ◽  
Power Efficiency ◽  
Average Power ◽  
Power Saving ◽  
Active State ◽  
Battery Lifetime ◽  
Accurate Model ◽  
Average Power Consumption

Currently, there is lack of implementation of practical power-saving schemes in most of the batteries powered by IoT smart city applications available in the market that can extend the battery lifetime, even though numerous researches have been carried to reduce the average power consumption. This is because electronics consume similar amounts of power during the idling state as compared to the active state, resulting in low power efficiency of the application. Thus, power consumption is affected by the modes of the electronic operations. Different electronics also have their own types of settings that can be configured to reduce the power consumption, and this will be further investigated in this study. This chapter will address the issue of how to create a power-saving IoT application by applying power-saving schemes and creating an accurate model to predict the battery lifetime of the IoT application.

A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications

2020 ◽  
Vol 12 (6) ◽  
pp. 825-830
Author(s):  
Abhijit Kumar Mukhopadhyay
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Large Scale ◽  
Average Power ◽  
Higher Order ◽  
Average Power Consumption ◽  
Xnor Gate ◽  
Large Scale Integration ◽  
Mathematical Equations ◽  
Scale Integration

This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.

scholarly journals The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI Designs AT 32NM Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 361-366
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Full Adder ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors

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