Aplicação do Filtro de Kalman Estendido com matrizes pré sintonizadas ao acionamento sensorless de motores de indução

2020 ◽  
Author(s):  
Leonardo De Magalhães Lopes ◽  
Zélia Myriam Assis Peixoto
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Control Technique ◽  
Reduced Order ◽  
Variance Matrix ◽  
Ac Electric Drive ◽  
Three Phase ◽  
High Performance Systems ◽  
Drive Systems ◽  
Signal Processors

Sensorless control methods stand out as an alternative for cost reduction and maintenance in AC electric drive systems. This work deals with the application of the Extended Kalman Filter (EKF) to the estimation of the speed and position of the rotor aiming at the implementation of the indirect vector control technique in a speed control system for three- phase induction motors. The Kalman lter, despite its mathematical and computational complexity, performs well under variable speed and load conditions as well as convergence times consistent with the usual requirements of high performance systems. The main contributions of this work are the use of a reduced-order EKF (ROEKF) and the co-variance matrix pretuning in order to accelerate the convergence in the velocity and position estimates for futureimplementations in digital signal processors currently accessible.

scholarly journals Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

2019 ◽  
Vol 8 (9) ◽  
pp. 2007-2014
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Arithmetic Operation ◽  
Digital Signal ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Digital Circuit Design ◽  
Unit Design ◽  
High Performance Systems ◽  
Signal Processors

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

scholarly journals Efficiency Comparison of 2-Level SiC Inverter and Soft Switching-Snubber SiC Inverter for Electric Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1690
Author(s):  
Marco di Benedetto ◽  
Luca Bigarelli ◽  
Alessandro Lidozzi ◽  
Luca Solero
Keyword(s):  
Conversion Efficiency ◽  
Electric Motor ◽  
High Performance ◽  
Power Converter ◽  
Power Cable ◽  
Electric Motor Drives ◽  
Snubber Circuit ◽  
Three Phase ◽  
Efficiency Comparison ◽  
Drive Systems

This paper focuses on the investigation and implementation of a high-performance power conversion system to reduce the overvoltage phenomenon in variable speed electric drive applications. Particularly, the pros and cons of using Silicon Carbide power MOSFETs in the power converter when a long power cable is employed in electric motor drive systems has been addressed. The three-phase two level inverter with the addition of snubber circuits that consist of capacitors and diodes has been investigated, designed and tested in order to mitigate the overvoltage problems without sacrificing the conversion efficiency. Given that the snubber circuit added to the switches can increase losses, an additional circuit is used to recover the energy from the snubber circuit. The proposed analysis has been then validated through an experimental campaign performed on the converter prototype. The experimental results show that the proposed converter can reduce the overvoltage at the electric motor terminals with excellent conversion efficiency compared to the classical solution like the three-phase two level inverter.

Introduction to Audio and Speech Signal Processing

2011 ◽  
pp. 1-20
Author(s):  
Hector Perez-Meana ◽  
Mariko Nakano-Miyatake
Keyword(s):  
Signal Processing ◽  
Hearing Aids ◽  
Speech Signal ◽  
High Performance ◽  
Digital Signal ◽  
Speech Signal Processing ◽  
Signal Processing Algorithms ◽  
Important Amount ◽  
Processing Algorithms ◽  
Signal Processors

The development of very efficient digital signal processors has allowed the implementation of high performance signal processing algorithms to solve an important amount of practical problems in several engineering fields, such as telecommunications, in which very efficient algorithms have been developed to storage, transmission, and interference reductions; in the audio field, where signal processing algorithms have been developed to enhancement, restoration, copy right protection of audio materials; in the medical field, where signal processing algorithms have been efficiently used to develop hearing aids systems and speech restoration systems for alaryngeal speech signals. This chapter presents an overview of some successful audio and speech signal processing algorithms, providing to the reader an overview of this important technology, some of which will be analyzed with more detail in the accompanying chapters of this book.

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