scholarly journals Novel Technique to Implement Low Power Differential Delay Cell Ring VCO with Variable Centre Frequency

2019 ◽  
Vol 8 (4) ◽  
pp. 5409-5416
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Research Work ◽  
Center Frequency ◽  
Variable Frequency ◽  
Differential Delay ◽  
Delay Cell ◽  
Noise Characteristics

Ring VCO with variable center frequency incorporating the design of differential delay cell working at low power is illustrated in the current research work. Concept of variable frequency with low power consumption is a novel VCO implementation technique. A differential delay cell is used to generate variable frequency to design a ring VCO at 32 nm technology operated at 1.2 V power supply voltage to achieve low power and low phase noise characteristics. Five stage ring VCO is designed with switches, to ensure that one stage works at a time, keeping two stages off. This switching of stages is dependend on the desired frequency of operation by the VCO. The proposed research work also facilitate the additional computation of width and length of PMOS and NMOS transistor along with the computation of optimal parameters. At 1 MHz offset frequency, the proposed VCO achieves phase noise of - 105.53 dBc/Hz with minimum power consumption of 1 mW. The proposed VCO is poised to act as a major building block of a multi-standard wireless communication system such as GSM, Blue tooth, and 802.11g ZigBee applications.

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750184 ◽  
Author(s):  
Qiuzhen Wan ◽  
Jun Dong ◽  
Hui Zhou ◽  
Fei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Current Reuse ◽  
Quadrature Vco ◽  
In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

scholarly journals Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System

2021 ◽  
Vol 11 (3) ◽  
pp. 1059
Author(s):  
Min-Su Kim ◽  
Sang-Sun Yoo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Low Energy ◽  
Superior Performance ◽  
Bluetooth Low Energy ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise

This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz.

scholarly journals A Low Power Voltage Controlled Oscillator Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Manoj Kumar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Nand Gate ◽  
Frequency Variation ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Voltage Controlled Oscillators ◽  
Delay Cell ◽  
Voltage Variation

The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 μW to 486.1816 μW. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 μW to 810.3027 μW. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 μW to 1134.400 μW. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz–6.1 GHz Applications in 0.18 μm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950182 ◽  
Author(s):  
Nitin Kumar ◽  
Manoj Kumar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Control Voltage ◽  
Cmos Process ◽  
Output Frequency ◽  
Differential Ring ◽  
Low Phase Noise ◽  
High Output

The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[Formula: see text]m CMOS process with a supply voltage ([Formula: see text]) 1.8[Formula: see text]V. The proposed design achieves an output frequency range of 4.029[Formula: see text]GHz to 6.122[Formula: see text]GHz and power of 4.475[Formula: see text]mW is consumed with control voltage variation from 1[Formula: see text]V to 2[Formula: see text]V. The proposed VCO exhibits [Formula: see text]89.7[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset frequency and the corresponding figure of merit (FoM) is [Formula: see text]155.9[Formula: see text]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.

Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique

2014 ◽  
Vol 6 (6) ◽  
pp. 573-580 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Po-Hung Chen ◽  
Yao-Yen Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Measurement Results ◽  
Low Power Cmos ◽  
5 Ghz ◽  
Low Phase Noise ◽  
Manufacture Company

In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

Low power consumption and low phase noise 2.4 GHz VCO using SiGe HBT for WLL application

1997 ◽  
Vol 33 (12) ◽  
pp. 1089 ◽  
Author(s):  
D.-H. Cho ◽  
B.R. Ryum ◽  
T.-H. Han ◽  
S.-M. Lee ◽  
K.-W. Yeom ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Low Power Consumption ◽  
Sige Hbt ◽  
Low Phase Noise

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

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